公开(公告)号：US09224655B2

公开(公告)日：2015-12-29

申请号：US13792540

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/311 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

Abstract translation: 本文公开的一种说明性方法包括以下步骤：形成覆盖P型晶体管并暴露N型晶体管的至少栅极帽层的掩模层，通过掩模层执行第一蚀刻工艺以去除部分 N型晶体管的栅极帽，从而限定了用于N型晶体管的减小厚度的栅极盖层，去除掩模层，并对P型晶体管和N型晶体管执行公共的第二蚀刻工艺 其去除了N型晶体管的P型晶体管的栅极盖层和减小厚度的栅极盖。

公开(公告)号：US20150348849A1

公开(公告)日：2015-12-03

申请号：US14294467

申请日：2014-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Gerd Zschaetzsch

IPC: H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/45 ,  H01L21/285 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

Abstract translation: 提供了一种形成晶体管器件的方法，包括随后执行的步骤，在第一半导体层上形成栅电极，在栅电极和第一半导体层上形成层间电介质，在层间电介质中形成第一开口 在栅电极的一侧上与栅电极横向间隔开的预定距离，并且在栅极电极的另一侧与栅电极横向间隔开预定距离的层间电介质中的第二开口，第一和第二开口到达第一 半导体层，通过形成在层间电介质中的第一和第二开口在第一半导体层中形成空腔，以及在空腔中形成嵌入的第二半导体层。

公开(公告)号：US20150179753A1

公开(公告)日：2015-06-25

申请号：US14136815

申请日：2013-12-20

Applicant: Globalfoundries Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Maciej Wiatr ,  Christian Schippel

IPC: H01L29/49 ,  H01L21/285 ,  H01L23/62

CPC classification number: H01L29/4975 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

Abstract translation: 电子熔断器用于集成电路，以便在制造后允许电路的实时动态重新编程。 因此提出了一种电熔丝，其中适于在电流通过时被吹塑的金属元件不是由硅化物层组成的，而是一个金属层，其上形成半导体层。 然后在半导体层上形成电介质层，以防止在金属层上形成金属硅化物。 电子熔断器的制造过程可以很容易地集成在HKMG制造流程中。 特别地，完全硅化金属栅极可以与电熔丝一起制造，而不会危及电子熔丝的正确功能。

公开(公告)号：US09012956B2

公开(公告)日：2015-04-21

申请号：US13783517

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823418 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

Abstract translation: 当形成复杂的P沟道晶体管时，在包括晶体管有源区的半导体层的表面上形成半导体合金层。 当与该半导体合金层邻接形成金属硅化物层时，观察到金属硅化物层与分离的团簇的聚集。 为了解决这个问题，本发明提出一种方法和半导体器件，其中在形成金属硅化物层之前去除位于晶体管的源极和漏极区域上的半导体合金层的部分。 以这种方式，金属硅化物层形成为与半导体层邻接，而不形成为半导体合金层。

公开(公告)号：US08963208B2

公开(公告)日：2015-02-24

申请号：US13678054

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Matthias Kessler ,  Jan Hoentschel

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66 ,  H01L27/12 ,  H01L27/06 ,  H01L29/94 ,  H01L27/088

CPC classification number: H01L21/84 ,  H01L21/02428 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/861 ,  H01L29/945

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

公开(公告)号：US20140357042A1

公开(公告)日：2014-12-04

申请号：US13907362

申请日：2013-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/266

CPC classification number: H01L29/6653 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28008 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/7833

Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.

Abstract translation: 制造晶体管时的已知问题是由间隔物不期望地引入晶体管沟道区域的应力。 为了解决这个问题，本发明提出了一种旨在缓和间隔物材料的应力的离子注入。 在间隔件已经完全形成之后进行松弛植入。 松弛植入可以在硅化处理之后或在源极和漏极区域中的注入步骤之后进行激活退火并且在进行硅化处理之前进行。

公开(公告)号：US08877582B2

公开(公告)日：2014-11-04

申请号：US13771294

申请日：2013-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Stefan Flachowsky ,  Nicolas Sassiat

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/7847

Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

Abstract translation: 这里的一种方法包括在半导体衬底的有源区上方形成栅极结构，形成与栅极结构相邻的侧壁间隔结构，形成允许将离子注入栅电极但不进入有源区的源的/ 将形成用于晶体管的漏极区域，执行栅极离子注入工艺以在栅极电极中形成栅极离子注入区域并执行退火工艺。 一种N型晶体管，其包括邻近栅极结构定位的侧壁间隔结构，用于晶体管的多个源极/漏极区域和位于栅极电极中的栅极注入区域，其中栅极注入区域由磷，砷或 原子尺寸等于或大于磷离子浓度在5e18-5e21离子/ cm3范围内的原子尺寸的植入材料。

公开(公告)号：US20140319620A1

公开(公告)日：2014-10-30

申请号：US13874200

申请日：2013-04-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括第一晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第一功函数材料层，设置在第一功函数材料层上的第二功函数材料层，以及 设置在第二功函数材料层上的金属填充材料。 集成电路还包括第二晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第二功函件层，以及设置在第二功函数材料上的金属填充材料层 层。 此外，集成电路包括电阻器结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的金属填充材料层以及设置在金属填充材料层上的硅材料层。

公开(公告)号：US20140252557A1

公开(公告)日：2014-09-11

申请号：US13788719

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L21/308 ,  H01L29/06

CPC classification number: H01L21/3083 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract translation: 提供了用于形成半导体器件的半导体器件结构和方法。 在实施例中，提供一个或多个翅片，所述一个或多个翅片中的每一个具有设置在下部的下部和上部。 下部嵌入第一绝缘材料中。 上部的形状是基本上三角形形状和大致圆形形状和大致梯形形状中的至少一个。 此外，在上部形成有与第一绝缘材料不同的第二绝缘材料层。

公开(公告)号：US20140252481A1

公开(公告)日：2014-09-11

申请号：US13792950

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

Abstract translation: 半导体结构包括衬底和晶体管。 晶体管包括设置在衬底上方的升高的源极区域和升高的漏极区域，一个或多个细长半导体管线，栅极电极和栅极绝缘层。 所述一个或多个细长半导体线连接在所述升高的源极区域和所述隆起的漏极区域之间，其中所述一个或多个细长半导体线路中的每一个的纵向方向基本上沿着垂直于所述衬底的厚度方向的水平方向延伸 。 每个细长半导体线包括沟道区。 栅电极围绕一个或多个细长半导体线路的每个沟道区域延伸。 栅极绝缘层设置在一个或多个细长半导体线路和栅电极中的每一个之间。