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    TRANSISTOR WITH EMBEDDED STRESS-INDUCING LAYERS
    1.
    发明申请
    TRANSISTOR WITH EMBEDDED STRESS-INDUCING LAYERS 有权
    具有嵌入式应力诱导层的晶体管

    公开(公告)号：US20150348849A1

    公开(公告)日：2015-12-03

    申请号：US14294467

    申请日：2014-06-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Gerd Zschaetzsch

    IPC: H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/45 ,  H01L21/285 ,  H01L29/78 ,  H01L21/02

    CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

    Abstract translation: 提供了一种形成晶体管器件的方法，包括随后执行的步骤，在第一半导体层上形成栅电极，在栅电极和第一半导体层上形成层间电介质，在层间电介质中形成第一开口 在栅电极的一侧上与栅电极横向间隔开的预定距离，并且在栅极电极的另一侧与栅电极横向间隔开预定距离的层间电介质中的第二开口，第一和第二开口到达第一 半导体层，通过形成在层间电介质中的第一和第二开口在第一半导体层中形成空腔，以及在空腔中形成嵌入的第二半导体层。

    Transistor with embedded stress-inducing layers
    5.
    发明授权
    Transistor with embedded stress-inducing layers 有权
    具有嵌入式应力诱导层的晶体管

    公开(公告)号：US09214396B1

    公开(公告)日：2015-12-15

    申请号：US14294467

    申请日：2014-06-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Gerd Zschaetzsch

    IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/45 ,  H01L21/285 ,  H01L21/265

    CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

    Abstract translation: 提供了一种形成晶体管器件的方法，包括随后执行的步骤，在第一半导体层上形成栅电极，在栅电极和第一半导体层上形成层间电介质，在层间电介质中形成第一开口 在栅电极的一侧上与栅电极横向间隔开的预定距离，并且在栅极电极的另一侧与栅电极横向间隔开预定距离的层间电介质中的第二开口，第一和第二开口到达第一 半导体层，通过形成在层间电介质中的第一和第二开口在第一半导体层中形成空腔，以及在空腔中形成嵌入的第二半导体层。

    FULLY SILICIDED GATE FORMED ACCORDING TO THE GATE-FIRST HKMG APPROACH
    6.
    发明申请
    FULLY SILICIDED GATE FORMED ACCORDING TO THE GATE-FIRST HKMG APPROACH 有权
    完整的硅胶门，根据第一次HKMG方法

    公开(公告)号：US20150050787A1

    公开(公告)日：2015-02-19

    申请号：US13965860

    申请日：2013-08-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Stefan Flachowsky ,  Gerd Zschaetzsch ,  Jan Hoentschel

    IPC: H01L29/66

    CPC classification number: H01L21/28097 ,  H01L21/8238 ,  H01L21/823835 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/6659

    Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.

    Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 然而，完全硅化的栅极的形成受到源极和漏极区域以及栅极电极的硅化同时正常执行的事实的阻碍。 所要求保护的方法提出了两个相互连接的硅化过程。 在第一硅化工艺期间，形成金属硅化物，形成与源区和漏区的界面，而不影响栅电极。 在第二硅化处理期间，形成与栅电极具有界面的金属硅化物层，而不会影响晶体管的源极和漏极区域。

    Fully silicided gate formed according to the gate-first HKMG approach
    9.
    发明授权
    Fully silicided gate formed according to the gate-first HKMG approach 有权
    根据门第一HKMG方法形成的全硅化物门

    公开(公告)号：US09218976B2

    公开(公告)日：2015-12-22

    申请号：US13965860

    申请日：2013-08-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Stefan Flachowsky ,  Gerd Zschaetzsch ,  Jan Hoentschel

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49

    CPC classification number: H01L21/28097 ,  H01L21/8238 ,  H01L21/823835 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/6659

    Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.

    Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 然而，完全硅化的栅极的形成受到源极和漏极区域以及栅极电极的硅化同时正常执行的事实的阻碍。 所要求保护的方法提出了两个相互连接的硅化过程。 在第一硅化工艺期间，形成金属硅化物，形成与源区和漏区的界面，而不影响栅电极。 在第二硅化处理期间，形成与栅电极具有界面的金属硅化物层，而不会影响晶体管的源极和漏极区域。

    Highly conformal extension doping in advanced multi-gate devices
    10.
    发明授权
    Highly conformal extension doping in advanced multi-gate devices 有权
    先进的多栅极器件中的高共形扩展掺杂

    公开(公告)号：US09209274B2

    公开(公告)日：2015-12-08

    申请号：US13946103

    申请日：2013-07-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Gerd Zschaetzsch ,  Stefan Flachowsky ,  Dominic Thurmer

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/8234

    CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

    Abstract: The present disclosure provides in various aspects methods of forming a semiconductor device, methods for forming a semiconductor device structure, a semiconductor device and a semiconductor device structure. In some illustrative embodiments herein, a gate structure is formed over a non-planar surface portion of a semiconductor material provided on a surface of a substrate. A doped spacer-forming material is formed over the gate structure and the semiconductor material and dopants incorporated in the doped spacer-forming material are diffused into the semiconductor material close to a surface of the semiconductor material so as to form source/drain extension regions. The fabricated semiconductor devices may be multi-gate devices and, for example, comprise finFETs and/or wireFETs.

    Abstract translation: 本公开在各方面提供了形成半导体器件的方法，形成半导体器件结构的方法，半导体器件和半导体器件结构。 在本文的一些说明性实施例中，栅极结构形成在设置在基板的表面上的半导体材料的非平面表面部分上。 掺杂的间隔物形成材料形成在栅极结构上，并且半导体材料和并入掺杂的间隔物形成材料中的掺杂剂被扩散到靠近半导体材料的表面的半导体材料中，以形成源极/漏极延伸区域。 制造的半导体器件可以是多栅极器件，并且例如包括finFET和/或wireFET。

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