公开(公告)号：US20150028263A1

公开(公告)日：2015-01-29

申请号：US13987450

申请日：2013-07-26

申请人： Yanbo Wang ,  Bor Z. Jang ,  Aruna Zhamu

发明人： Yanbo Wang ,  Bor Z. Jang ,  Aruna Zhamu

IPC分类号： H01M4/38 ,  H01M4/62

CPC分类号： H01M4/364 ,  H01M4/386 ,  H01M4/587 ,  H01M4/625 ,  H01M10/052 ,  H01M2004/027

摘要： Disclosed is a facile and cost effective method of producing nano silicon powder or graphene-doped silicon nano powder having a particle size smaller than 100 nm. The method comprises: (a) preparing a silicon precursor/graphene nano composite; (b) mixing the silicon precursor/graphene nano composite with a desired quantity of magnesium; (c) converting the silicon precursor to form a mixture of graphene-doped silicon and a reaction by-product through a thermal and/or chemical reduction reaction; and (d) removing the reaction by-product from the mixture to obtain graphene-doped silicon nano powder.

摘要翻译： 公开了一种制造具有小于100nm的粒度的纳米硅粉末或石墨烯掺杂的硅纳米粉末的简便和成本有效的方法。 该方法包括：（a）制备硅前体/石墨烯纳米复合材料; （b）将硅前体/石墨烯纳米复合材料与所需量的镁混合; （c）通过热和/或化学还原反应转化硅前体以形成掺杂有石墨烯的硅和反应副产物的混合物; 和（d）从混合物中除去反应副产物以获得石墨烯掺杂的硅纳米粉末。

公开(公告)号：US20140315100A1

公开(公告)日：2014-10-23

申请号：US13986319

申请日：2013-04-22

申请人： Yanbo Wang ,  Bor Z. Jang ,  Hui He ,  Aruna Zhamu ,  Yi-jun Lin

发明人： Yanbo Wang ,  Bor Z. Jang ,  Hui He ,  Aruna Zhamu ,  Yi-jun Lin

IPC分类号： H01M4/36

CPC分类号： H01M4/366 ,  H01M4/136 ,  H01M4/1397 ,  H01M4/621 ,  H01M4/625 ,  H01M10/3909 ,  H01M2004/021 ,  Y10T29/49115

摘要： A rechargeable lithium-sulfur cell comprising an anode, a separator and/or electrolyte, a sulfur cathode, an optional anode current collector, and an optional cathode current collector, wherein the cathode comprises (a) exfoliated graphite worms that are interconnected to form a porous, conductive graphite flake network comprising pores having a size smaller than 100 nm; and (b) nano-scaled powder or coating of sulfur, sulfur compound, or lithium polysulfide disposed in the pores or coated on graphite flake surfaces wherein the powder or coating has a dimension less than 100 nm. The exfoliated graphite worm amount is in the range of 1% to 90% by weight and the amount of powder or coating is in the range of 99% to 10% by weight based on the total weight of exfoliated graphite worms and sulfur (sulfur compound or lithium polysulfide) combined. The cell exhibits an exceptionally high specific energy and a long cycle life.

摘要翻译： 包括阳极，隔板和/或电解质，硫阴极，任选的阳极集电器和任选的阴极集电器的可再充电锂 - 硫电池，其中所述阴极包括（a）相互连接形成的剥离的石墨蠕虫 多孔导电石墨薄片网络，其包含尺寸小于100nm的孔; 和（b）设置在孔中的纳米级粉末或硫，硫化合物或多硫化锂的涂层，或涂覆在石墨片表面上，其中粉末或涂层具有小于100nm的尺寸。 剥离石墨蠕虫量在1重量％至90重量％的范围内，粉末或涂层的量基于脱落的石墨蠕虫和硫（硫化合物）的总重量在99重量％至10重量％的范围内 或多硫化锂）组合。 电池表现出特别高的比能量和较长的循环寿命。

公开(公告)号：US20130302697A1

公开(公告)日：2013-11-14

申请号：US13506736

申请日：2012-05-14

申请人： Yanbo Wang ,  Aruna Zhamu ,  Bor Z. Jang

发明人： Yanbo Wang ,  Aruna Zhamu ,  Bor Z. Jang

IPC分类号： H01M4/64 ,  H01M10/054 ,  B82Y30/00

CPC分类号： H01M10/054 ,  B82Y30/00 ,  H01G11/36 ,  H01G11/56 ,  H01M4/0445 ,  H01M4/466 ,  H01M4/485 ,  H01M4/5815 ,  H01M4/5825 ,  H01M4/587 ,  H01M10/446 ,  Y02E60/122 ,  Y02E60/13

摘要： A magnesium-ion cell comprising (a) a cathode comprising a carbon or graphitic material as a cathode active material having a surface area to capture and store magnesium thereon, wherein the cathode forms a meso-porous structure having a pore size from 2 nm to 50 nm and a specific surface area greater than 50 m2/g; (b) an anode comprising an anode current collector alone or a combination of an anode current collector and an anode active material; (c) a porous separator disposed between the anode and the cathode; (d) electrolyte in ionic contact with the anode and the cathode; and (e) a magnesium ion source disposed in the anode to obtain an open circuit voltage (OCV) from 0.5 volts to 3.5 volts when the cell is made.

摘要翻译： 一种镁离子电池，其包含（a）包含碳或石墨材料作为阴极活性材料的阴极，所述阴极活性材料具有捕获并存储镁的表面积，其中所述阴极形成孔径为2nm至 50nm，比表面积大于50m2 / g; （b）阳极，其包括单独的阳极集电器和阳极集电器和负极活性材料的组合; （c）设置在阳极和阴极之间的多孔隔板; （d）与阳极和阴极离子接触的电解质; 和（e）设置在阳极中的镁离子源，以在制造电池时获得从0.5伏至3.5伏的开路电压（OCV）。

公开(公告)号：US20140342209A1

公开(公告)日：2014-11-20

申请号：US13986575

申请日：2013-05-16

申请人： Hui He ,  Boz Z Jang ,  Yanbo Wang ,  Aruna Zhamu ,  Wei Xiong

发明人： Hui He ,  Boz Z Jang ,  Yanbo Wang ,  Aruna Zhamu ,  Wei Xiong

IPC分类号： H01M10/056 ,  H01M10/052

CPC分类号： H01M10/056 ,  H01M4/134 ,  H01M4/136 ,  H01M4/38 ,  H01M4/382 ,  H01M4/5815 ,  H01M4/663 ,  H01M4/668 ,  H01M4/747 ,  H01M4/80 ,  H01M4/806 ,  H01M10/052 ,  H01M10/0566 ,  H01M2300/0025 ,  Y02E60/122 ,  Y02T10/7011

摘要： A rechargeable lithium-sulfur cell comprising a cathode, an anode, a separator electronically separating the two electrodes, a first electrolyte in contact with the cathode, and a second electrolyte in contact with the anode, wherein the first electrolyte contains a first concentration, C1, of a first lithium salt dissolved in a first solvent when the first electrolyte is brought in contact with the cathode, and the second electrolyte contains a second concentration, C2, of a second lithium salt dissolved in a second solvent when the second electrolyte is brought in contact with the anode, wherein C1 is less than C2. The cell exhibits an exceptionally high specific energy and a long cycle life.

摘要翻译： 一种可再充电锂硫电池，包括阴极，阳极，电子分离两个电极的隔板，与阴极接触的第一电解质和与阳极接触的第二电解质，其中第一电解质含有第一浓度，C1 当第一电解质与阴极接触时溶解在第一溶剂中的第一锂盐，当第二电解质带入时，第二电解质含有溶解在第二溶剂中的第二锂盐的第二浓度C2 与阳极接触，其中C1小于C2。 电池表现出特别高的比能量和较长的循环寿命。

公开(公告)号：US08861669B2

公开(公告)日：2014-10-14

申请号：US12571210

申请日：2009-09-30

申请人： Xiaoqian Zhang ,  Shubing Zhai ,  Yanbo Wang

发明人： Xiaoqian Zhang ,  Shubing Zhai ,  Yanbo Wang

IPC分类号： H03D3/24 ,  H03L7/197 ,  H04N21/43 ,  H03L7/193 ,  H04N21/41 ,  H04J3/06 ,  G09G5/00

CPC分类号： H04J3/062 ,  G09G5/008 ,  H03L7/193 ,  H03L7/1978 ,  H04N21/4122 ,  H04N21/4307

摘要： The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.

摘要翻译： 本公开提供了用于在高清晰度多媒体数字内容传输系统中的信宿处恢复源流时钟数据的技术。 本公开包括基于分数N锁相环（PLL）的时钟发生器，可编程Σ-Δ调制器（SDM）和时钟数据校准器，以完全恢复原始源流时钟数据。 分数N PLL提供灵活的源流时钟恢复。 当原始时钟与再生时钟之间存在频率偏差时，时钟数据校准器控制电路调整时钟数据，防止任何流数据缓冲区溢出或下溢问题。 所公开的技术基于DisplayPort和HDMI的标准与宿设备兼容。

公开(公告)号：US20090237132A1

公开(公告)日：2009-09-24

申请号：US12077929

申请日：2008-03-20

申请人： Yanbo Wang ,  Xiaoqian Zhang ,  Shubing Zhai

发明人： Yanbo Wang ,  Xiaoqian Zhang ,  Shubing Zhai

IPC分类号： H03L7/085

CPC分类号： H03L7/18 ,  H03L7/0891

摘要： A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

摘要翻译： 一种校准PLL的方法，其包括强制输入到压控振荡器的控制电压作为参考电压，并且设置耦合以从压控振荡器接收输出时钟信号的校准分配器，使得校准分配器利用多个 导致输出时钟信号具有高频率的除数可以基本上避免与常规PLL校准相关的过冲和毛刺问题。

公开(公告)号：US20110075782A1

公开(公告)日：2011-03-31

申请号：US12571210

申请日：2009-09-30

申请人： Xiaoqian Zhang ,  Shubing Zhai ,  Yanbo Wang

发明人： Xiaoqian Zhang ,  Shubing Zhai ,  Yanbo Wang

IPC分类号： H04L7/00

CPC分类号： H04J3/062 ,  G09G5/008 ,  H03L7/193 ,  H03L7/1978 ,  H04N21/4122 ,  H04N21/4307

摘要： The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.

摘要翻译： 本公开提供了用于在高清晰度多媒体数字内容传输系统中的信宿处恢复源流时钟数据的技术。 本公开包括基于分数N锁相环（PLL）的时钟发生器，可编程Σ-Δ调制器（SDM）和时钟数据校准器，以完全恢复原始源流时钟数据。 分数N PLL提供灵活的源流时钟恢复。 当原始时钟与再生时钟之间存在频率偏差时，时钟数据校准器控制电路调整时钟数据，防止任何流数据缓冲区溢出或下溢问题。 所公开的技术基于DisplayPort和HDMI的标准与宿设备兼容。

公开(公告)号：US07436224B2

公开(公告)日：2008-10-14

申请号：US11494847

申请日：2006-07-27

申请人： Yanbo Wang ,  Hongquan Wang ,  Xuexin Ding

发明人： Yanbo Wang ,  Hongquan Wang ,  Xuexin Ding

IPC分类号： H03B1/00

CPC分类号： H03K19/00384

摘要： The methods and systems presented herein provide an improved means of correcting the variation of Voltage Output Differential (VOD) in differential drivers. In some embodiments, a high-precision reference voltage is generated not only based on a desired VOD, but also by monitoring the Voltage Common Mode (VCM) in a differential driver. In some embodiments, the VOD is then compared with the high-precision reference voltage to correct the output current. The result is a low-variation output voltage.

公开(公告)号：US20100007397A1

公开(公告)日：2010-01-14

申请号：US12218457

申请日：2008-07-11

申请人： Shengyuan Zhang ,  Yong Wang ,  Yanbo Wang

发明人： Shengyuan Zhang ,  Yong Wang ,  Yanbo Wang

IPC分类号： H03H11/26 ,  H03K3/011 ,  G05F1/00

CPC分类号： G05F3/30 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00078

摘要： A delay line circuit is provided. The delay line circuit includes a reference voltage generating circuit that generates a reference voltage, the reference voltage having a positive temperature coefficient. The delay line circuit also includes a voltage regulating circuit that generates a regulated voltage in response to the generated reference voltage as an input, and a delay chain circuit coupled to the voltage regulator to receive the regulated voltage, the delay chain circuit outputting a delay signal. In an embodiment consistent with the present invention, the reference voltage generating circuit includes a bandgap reference voltage circuit. In another embodiment consistent with the present invention, the reference voltage generating circuit includes a proportional to absolute temperature (PTAT) circuit.

摘要翻译： 提供延迟线电路。 延迟线电路包括产生参考电压的参考电压产生电路，该参考电压具有正温度系数。 延迟线电路还包括电压调节电路，其响应于产生的参考电压作为输入而产生调节电压，以及延迟链电路，耦合到电压调节器以接收调节电压，延迟链电路输出延迟信号 。 在与本发明一致的实施例中，参考电压产生电路包括带隙基准电压电路。 在与本发明一致的另一实施例中，参考电压产生电路包括与绝对温度（PTAT）成比例的电路。

公开(公告)号：US07750696B2

公开(公告)日：2010-07-06

申请号：US12077929

申请日：2008-03-20

申请人： Yanbo Wang ,  Xiaoqian Zhang ,  Shubing Zhai

发明人： Yanbo Wang ,  Xiaoqian Zhang ,  Shubing Zhai

IPC分类号： H03L7/06

CPC分类号： H03L7/18 ,  H03L7/0891

摘要： A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

摘要翻译： 一种校准PLL的方法，其包括强制输入到压控振荡器的控制电压作为参考电压，并且设置耦合以从压控振荡器接收输出时钟信号的校准分配器，使得校准分配器利用多个 导致输出时钟信号具有高频率的除数可以基本上避免与常规PLL校准相关的过冲和毛刺问题。