公开(公告)号：US07935583B2

公开(公告)日：2011-05-03

申请号：US11951321

申请日：2007-12-05

申请人： Shiun-Chang Jan ,  Han-Tu Lin

发明人： Shiun-Chang Jan ,  Han-Tu Lin

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A fabrication method of a pixel structure includes utilizing only a single photomask in two different lithographic processes for defining patterns of the source/drain and passivation layer respectively. Therefore, the total amount of photomasks of the fabrication process can be decreased.

摘要翻译： 像素结构的制造方法包括仅在两个不同的光刻工艺中使用单个光掩模来分别限定源极/漏极和钝化层的图案。 因此，可以减少制造工艺的光掩模的总量。

公开(公告)号：US07897449B2

公开(公告)日：2011-03-01

申请号：US12076681

申请日：2008-03-21

申请人： Han-Tu Lin ,  Chien-Hung Chen

发明人： Han-Tu Lin ,  Chien-Hung Chen

IPC分类号： H01L21/8238 ,  H01L29/04

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.

公开(公告)号：US07842954B2

公开(公告)日：2010-11-30

申请号：US12775493

申请日：2010-05-07

申请人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

发明人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

IPC分类号： H01L33/00

CPC分类号： H01L27/124 ,  H01L27/1248 ,  H01L27/1288

摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

摘要翻译： 设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。 图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。 图案化的半导体层设置在图案化的栅极绝缘层上。 第二图案化导电层设置在图案化的半导体层上。 图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。 透明导电层完全设置在基板上。 设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

公开(公告)号：US07834361B2

公开(公告)日：2010-11-16

申请号：US12591019

申请日：2009-11-05

申请人： Han-Tu Lin ,  Chien-Hung Chen

发明人： Han-Tu Lin ,  Chien-Hung Chen

IPC分类号： H01L29/04 ,  H01L21/8238

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.

公开(公告)号：US07829397B2

公开(公告)日：2010-11-09

申请号：US12400171

申请日：2009-03-09

申请人： Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

发明人： Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8238

CPC分类号： H01L29/66765 ,  H01L29/04 ,  H01L29/452 ,  H01L29/78678 ,  H01L29/78696

摘要： A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

摘要翻译： 底栅薄膜晶体管包括栅电极，栅极绝缘层和微晶硅层。 栅电极设置在基板上。 栅极绝缘层由氮化硅构成并且设置在栅电极和基板上。 微晶硅层设置在栅极绝缘层上，对应于栅电极，其中栅极绝缘层和微晶硅层之间的接触界面具有多个氧原子，氧原子的浓度范围在1020原子之间 / cm3和1025原子/ cm3。 本文还公开了制造底栅薄膜晶体管的方法。

公开(公告)号：US07786514B2

公开(公告)日：2010-08-31

申请号：US11964174

申请日：2007-12-26

申请人： Kuo-Lung Fang ,  Wen-Ching Tsai ,  Kuo-Yuan Tu ,  Han-Tu Lin

发明人： Kuo-Lung Fang ,  Wen-Ching Tsai ,  Kuo-Yuan Tu ,  Han-Tu Lin

IPC分类号： H01L29/76 ,  H01L27/148 ,  H01L29/768 ,  H01L31/062 ,  H01L31/00

CPC分类号： H01L29/4908 ,  H01L29/66765 ,  H01L29/78669

摘要： The invention discloses a switching device for a pixel electrode of display device. The switching device comprises a gate formed on a substrate; a gate-insulating layer formed on the gate; a first buffer layer formed between the substrate and the gate and/or between the gate and the gate-insulating layer, wherein the first buffer layer comprises TaSix, TaSixNy, TiSix, TiSixNy, WSix, WSixNy, or WCxNy; a semiconductor layer formed on a portion of the gate-insulating layer; and a source and a drain formed on a portion of the semiconductor layer.

摘要翻译： 本发明公开了一种用于显示装置的像素电极的开关装置。 开关装置包括形成在基板上的栅极; 形成在栅极上的栅极绝缘层; 形成在所述基板和所述栅极之间和/或所述栅极与所述栅极绝缘层之间的第一缓冲层，其中所述第一缓冲层包括TaSix，TaSixNy，TiSix，TiSixNy，WSix，WSixNy或WCxNy; 形成在所述栅极绝缘层的一部分上的半导体层; 以及形成在半导体层的一部分上的源极和漏极。

公开(公告)号：US20080258146A1

公开(公告)日：2008-10-23

申请号：US12146479

申请日：2008-06-26

申请人： Han-Tu Lin

发明人： Han-Tu Lin

IPC分类号： H01L29/786

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66765

摘要： A fabrication method of a TFT includes successively forming four thin films containing a first conductive layer, an insulation layer, a semiconductor layer, and a second conductive layer on a substrate, performing a first PEP process to pattern the four thin films for forming a semiconductor island and a gate electrode with the semiconductor layer and the first conductive layer respectively. Then, a laser ablation process is performed to define a channel pattern in the four thin films and remove a portion of the second conductive layer so that unconnected source electrode and drain electrode are formed with the second conductive layer.

摘要翻译： TFT的制造方法包括在基板上依次形成包含第一导电层，绝缘层，半导体层和第二导电层的四个薄膜，执行第一PEP工艺以对四个用于形成半导体的薄膜 岛和分别具有半导体层和第一导电层的栅电极。 然后，执行激光烧蚀处理以限定四个薄膜中的沟道图案，并去除第二导电层的一部分，使得未连接的源电极和漏电极与第二导电层形成。

公开(公告)号：US07413940B2

公开(公告)日：2008-08-19

申请号：US11530897

申请日：2006-09-11

申请人： Han-Tu Lin

发明人： Han-Tu Lin

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66765

摘要： A fabrication method of a TFT includes successively forming four thin films containing a first conductive layer, an insulation layer, a semiconductor layer, and a second conductive layer on a substrate, performing a first PEP process to pattern the four thin films for forming a semiconductor island and a gate electrode with the semiconductor layer and the first conductive layer respectively. Then, a laser ablation process is performed to define a channel pattern in the four thin films and remove a portion of the second conductive layer so that unconnected source electrode and drain electrode are formed with the second conductive layer.

摘要翻译： TFT的制造方法包括在基板上依次形成包含第一导电层，绝缘层，半导体层和第二导电层的四个薄膜，执行第一PEP工艺以对四个用于形成半导体的薄膜 岛和分别具有半导体层和第一导电层的栅电极。 然后，执行激光烧蚀处理以限定四个薄膜中的沟道图案，并去除第二导电层的一部分，使得未连接的源电极和漏电极与第二导电层形成。

公开(公告)号：US07411212B2

公开(公告)日：2008-08-12

申请号：US11247510

申请日：2005-10-11

申请人： Kuo-Lung Fang ,  Wen-Ching Tsai ,  Yeong-Shyang Lee ,  Han-Tu Lin

发明人： Kuo-Lung Fang ,  Wen-Ching Tsai ,  Yeong-Shyang Lee ,  Han-Tu Lin

IPC分类号： H01L29/04 ,  H01L31/20 ,  H01L31/036 ,  H01L31/0376 ,  H01L29/76

CPC分类号： H01L29/4908 ,  H01L29/66765

摘要： The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.

摘要翻译： 本发明公开了一种用于显示装置的像素电极的开关元件及其制造方法。 栅极形成在基板上。 在栅极上形成第一铜硅化物层。 在第一硅化铜层上形成绝缘层。 在绝缘层上形成半导体层。 源极和漏极形成在半导体层上。 此外，第二硅化铜层夹在半导体层和源极/漏极之间。

公开(公告)号：US20080158650A1

公开(公告)日：2008-07-03

申请号：US12038221

申请日：2008-02-27

申请人： Chia-Sheng Lee ,  Han-Tu Lin ,  Jia-Fam Wong

发明人： Chia-Sheng Lee ,  Han-Tu Lin ,  Jia-Fam Wong

IPC分类号： G02B26/00

CPC分类号： G02B26/001

摘要： A microelectromechanical optical display devices is provided. An optical layer is disposed on a substrate. A plurality of posts are disposed on the optical layer. A reflective layer is disposed on the plurality of posts. A flexible layer is disposed on the reflective layer, wherein edge of the reflective layer is separated from edge of the flexible layer by a distance equal to or smaller than about 2 μm.

摘要翻译： 提供了一种微机电光学显示装置。 光学层设置在基板上。 多个柱设置在光学层上。 反射层设置在多个柱上。 柔性层设置在反射层上，其中反射层的边缘与柔性层的边缘分开等于或小于约2μm的距离。