公开(公告)号：US08071409B2

公开(公告)日：2011-12-06

申请号：US12542703

申请日：2009-08-18

Applicant: Te-Chung Wang ,  Chun-Jong Chang ,  Kun-Fu Huang

Inventor： Te-Chung Wang ,  Chun-Jong Chang ,  Kun-Fu Huang

IPC: H01L21/00 ,  H01L33/00

CPC classification number: H01L33/007 ,  Y10S438/962 ,  Y10S977/755

Abstract: A fabrication method of light emitting diode is provided. A first type doped semiconductor layer is formed on a substrate. Subsequently, a light emitting layer is formed on the first type doped semiconductor layer. A process for forming the light emitting layer includes alternately forming a plurality of barrier layers and a plurality of quantum well layers on the first type doped semiconductor layer. The quantum well layers are formed at a growth temperature T1, and the barrier layers are formed at a growth temperature T2, where T1

Abstract translation: 提供了一种发光二极管的制造方法。 在基板上形成第一种类型的掺杂半导体层。 随后，在第一种掺杂半导体层上形成发光层。 形成发光层的工艺包括在第一掺杂半导体层上交替地形成多个势垒层和多个量子阱层。 量子阱层以生长温度T1形成，并且阻挡层以T1

公开(公告)号：US20110012114A1

公开(公告)日：2011-01-20

申请号：US12893063

申请日：2010-09-29

Applicant: Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

Inventor： Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

IPC: H01L29/786

CPC classification number: H01L29/66765 ,  H01L29/04 ,  H01L29/452 ,  H01L29/78678 ,  H01L29/78696

Abstract: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

Abstract translation: 底栅薄膜晶体管包括栅电极，栅极绝缘层和微晶硅层。 栅电极设置在基板上。 栅极绝缘层由氮化硅构成并且设置在栅电极和基板上。 微晶硅层设置在栅极绝缘层上，对应于栅电极，其中栅极绝缘层和微晶硅层之间的接触界面具有多个氧原子，氧原子的浓度范围在1020原子之间 / cm3和1025原子/ cm3。 本文还公开了制造底栅薄膜晶体管的方法。

公开(公告)号：US20120153339A1

公开(公告)日：2012-06-21

申请号：US13050677

申请日：2011-03-17

Applicant: JUN-RONG CHEN ,  CHI-WEN KUO ,  KUN-FU HUANG ,  JUI-YI CHU ,  KUO-LUNG FANG

Inventor： JUN-RONG CHEN ,  CHI-WEN KUO ,  KUN-FU HUANG ,  JUI-YI CHU ,  KUO-LUNG FANG

IPC: H01L33/36 ,  H01L33/20

CPC classification number: H01L33/20 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/382 ,  H01L33/387

Abstract: A light-emitting diode chip structure including a conductive substrate, a semiconductor stacking layer and a patterned seed crystal layer is provided. The conductive substrate has a surface. The surface has a first region and a second region alternately distributed over the surface. The semiconductor stacking layer is disposed on the conductive substrate, and the surface of the conductive substrate faces the semiconductor stacking layer. The patterned seed crystal layer is disposed on the first region of the surface of the conductive substrate and between the conductive substrate and the semiconductor stacking layer. The patterned seed crystal layer separates the semiconductor stacking layer from the first region. The semiconductor stacking layer covers the patterned seed crystal layer and the second region, and is electrically connected to the conductive substrate through the second region. A fabrication method of the light-emitting diode chip structure is also provided.

Abstract translation: 提供了包括导电基板，半导体堆叠层和图案化晶种层的发光二极管芯片结构。 导电基板具有表面。 表面具有交替地分布在表面上的第一区域和第二区域。 半导体层叠层设置在导电性基板上，导电性基板的表面面向半导体层叠层。 图案化晶种层设置在导电基板的表面的第一区域上，并且在导电基板和半导体堆叠层之间。 图案化晶种层将半导体层叠层与第一区域分开。 半导体堆叠层覆盖图案化晶种层和第二区域，并且通过第二区域电连接到导电基板。 还提供了发光二极管芯片结构的制造方法。

公开(公告)号：US08084771B2

公开(公告)日：2011-12-27

申请号：US12893063

申请日：2010-09-29

Applicant: Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

Inventor： Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

IPC: H01L29/04 ,  H01L31/036 ,  H01L27/01 ,  H01L27/12 ,  H01L31/20

CPC classification number: H01L29/66765 ,  H01L29/04 ,  H01L29/452 ,  H01L29/78678 ,  H01L29/78696

Abstract: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

Abstract translation: 底栅薄膜晶体管包括栅电极，栅极绝缘层和微晶硅层。 栅电极设置在基板上。 栅极绝缘层由氮化硅构成并且设置在栅电极和基板上。 微晶硅层设置在栅极绝缘层上，对应于栅电极，其中栅极绝缘层和微晶硅层之间的接触界面具有多个氧原子，氧原子的浓度范围在1020原子之间 / cm3和1025原子/ cm3。 本文还公开了制造底栅薄膜晶体管的方法。

公开(公告)号：US08253160B2

公开(公告)日：2012-08-28

申请号：US13050677

申请日：2011-03-17

Applicant: Jun-Rong Chen ,  Chi-Wen Kuo ,  Kun-Fu Huang ,  Jui-Yi Chu ,  Kuo-Lung Fang

Inventor： Jun-Rong Chen ,  Chi-Wen Kuo ,  Kun-Fu Huang ,  Jui-Yi Chu ,  Kuo-Lung Fang

IPC: H01L33/20

CPC classification number: H01L33/20 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/382 ,  H01L33/387

Abstract: A light-emitting diode chip structure including a conductive substrate, a semiconductor stacking layer and a patterned seed crystal layer is provided. The conductive substrate has a surface. The surface has a first region and a second region alternately distributed over the surface. The semiconductor stacking layer is disposed on the conductive substrate, and the surface of the conductive substrate faces the semiconductor stacking layer. The patterned seed crystal layer is disposed on the first region of the surface of the conductive substrate and between the conductive substrate and the semiconductor stacking layer. The patterned seed crystal layer separates the semiconductor stacking layer from the first region. The semiconductor stacking layer covers the patterned seed crystal layer and the second region, and is electrically connected to the conductive substrate through the second region. A fabrication method of the light-emitting diode chip structure is also provided.

Abstract translation: 提供了包括导电基板，半导体堆叠层和图案化晶种层的发光二极管芯片结构。 导电基板具有表面。 表面具有交替地分布在表面上的第一区域和第二区域。 半导体层叠层设置在导电性基板上，导电性基板的表面面向半导体层叠层。 图案化晶种层设置在导电基板的表面的第一区域上，并且在导电基板和半导体堆叠层之间。 图案化晶种层将半导体层叠层与第一区域分开。 半导体堆叠层覆盖图案化晶种层和第二区域，并且通过第二区域电连接到导电基板。 还提供了发光二极管芯片结构的制造方法。

公开(公告)号：US20120168712A1

公开(公告)日：2012-07-05

申请号：US13329704

申请日：2011-12-19

Applicant: Kuo-Lung Fang ,  Kun-Fu Huang ,  Chun-Jong Chang ,  Chi-Wen Kuo ,  Jun-Rong Chen ,  Chih-wei Chao

Inventor： Kuo-Lung Fang ,  Kun-Fu Huang ,  Chun-Jong Chang ,  Chi-Wen Kuo ,  Jun-Rong Chen ,  Chih-wei Chao

IPC: H01L33/04 ,  H01L33/60

CPC classification number: H01L33/382 ,  H01L33/46

Abstract: A high bright LED comprises a substrate, a conductive layer, a first semiconductor layer, a luminous layer, a second semiconductor layer, a first electrode, a second electrode and an insulation structure. The conductive layer, the first semiconductor layer, the luminous layer and the second semiconductor layer are disposed upwards from an upper solder layer of the substrate in order. The first electrode is electrically connected to the conductive layer The second electrode penetrates through the conductive layer, the first semiconductor layer and the luminous layer to make the upper solder and the second semiconductor layer electrically connected. The insulation structure comprises at least two passivation layers peripherally wrapping the second electrode. The thicknesses of the at least two passivation layers are conformed to the distributed Bragg reflection technique to make the passivation layers jointly used as a reflector with high reflectance.

Abstract translation: 高亮度LED包括基板，导电层，第一半导体层，发光层，第二半导体层，第一电极，第二电极和绝缘结构。 导电层，第一半导体层，发光层和第二半导体层依次从衬底的上焊料层向上设置。 第一电极电连接到导电层。第二电极穿过导电层，第一半导体层和发光层，以使上焊料和第二半导体层电连接。 绝缘结构包括至少两个钝化层，其外围地缠绕第二电极。 至少两个钝化层的厚度符合分布布拉格反射技术，以使钝化层联合用作具有高反射率的反射器。

公开(公告)号：US20110210343A1

公开(公告)日：2011-09-01

申请号：US12859825

申请日：2010-08-20

Applicant: Fu-Bang CHEN ,  Kuo-Lung Fang ,  Kun-Fu Huang ,  Te-Chung Wang

Inventor： Fu-Bang CHEN ,  Kuo-Lung Fang ,  Kun-Fu Huang ,  Te-Chung Wang

IPC: H01L33/00 ,  H01L23/00

CPC classification number: H01L33/12 ,  H01L33/007 ,  H01L33/20

Abstract: A semiconductor wafer includes a substrate, a first separating structure and a semiconductor stacked layer structure. The substrate has a first surface. The first separating structure is formed on the first surface to divide the first surface into a plurality of independent regions. The minimum area of each of the regions is more than or equal to one square inch. The semiconductor stacked layer structure is disposed on the first surface and the first separating structure. The semiconductor wafer can prevent bowing of the semiconductor wafer during an epitaxial growth process so as to enhance quality of the semiconductor wafer.

Abstract translation: 半导体晶片包括基板，第一分离结构和半导体叠层结构。 衬底具有第一表面。 第一分离结构形成在第一表面上以将第一表面分成多个独立区域。 每个区域的最小面积大于或等于1平方英寸。 半导体堆叠层结构设置在第一表面和第一分离结构上。 半导体晶片可以在外延生长工艺期间防止半导体晶片弯曲，从而提高半导体晶片的质量。

公开(公告)号：US20100285626A1

公开(公告)日：2010-11-11

申请号：US12542703

申请日：2009-08-18

Applicant: Te-Chung Wang ,  Chun-Jong Chang ,  Kun-Fu Huang

Inventor： Te-Chung Wang ,  Chun-Jong Chang ,  Kun-Fu Huang

IPC: H01L33/00

CPC classification number: H01L33/007 ,  Y10S438/962 ,  Y10S977/755

Abstract: A fabrication method of light emitting diode is provided. A first type doped semiconductor layer is formed on a substrate. Subsequently, a light emitting layer is formed on the first type doped semiconductor layer. A process for forming the light emitting layer includes alternately forming a plurality of barrier layers and a plurality of quantum well layers on the first type doped semiconductor layer. The quantum well layers are formed at a growth temperature T1, and the barrier layers are formed at a growth temperature T2, where T1

Abstract translation: 提供了一种发光二极管的制造方法。 在基板上形成第一种类型的掺杂半导体层。 随后，在第一种掺杂半导体层上形成发光层。 形成发光层的工艺包括在第一掺杂半导体层上交替地形成多个势垒层和多个量子阱层。 量子阱层以生长温度T1形成，并且阻挡层以T1

公开(公告)号：US07829397B2

公开(公告)日：2010-11-09

申请号：US12400171

申请日：2009-03-09

Applicant: Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

Inventor： Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L29/66765 ,  H01L29/04 ,  H01L29/452 ,  H01L29/78678 ,  H01L29/78696

Abstract: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

Abstract translation: 底栅薄膜晶体管包括栅电极，栅极绝缘层和微晶硅层。 栅电极设置在基板上。 栅极绝缘层由氮化硅构成并且设置在栅电极和基板上。 微晶硅层设置在栅极绝缘层上，对应于栅电极，其中栅极绝缘层和微晶硅层之间的接触界面具有多个氧原子，氧原子的浓度范围在1020原子之间 / cm3和1025原子/ cm3。 本文还公开了制造底栅薄膜晶体管的方法。

公开(公告)号：US20110318670A1

公开(公告)日：2011-12-29

申请号：US12964572

申请日：2010-12-09

Applicant: Jyun-Yi Lai ,  Yu-Chih Lin ,  Jiun-Ming Chen ,  Chi-Yuan Chen ,  Chiang-Wen Lai ,  Kun-Fu Huang

Inventor： Jyun-Yi Lai ,  Yu-Chih Lin ,  Jiun-Ming Chen ,  Chi-Yuan Chen ,  Chiang-Wen Lai ,  Kun-Fu Huang

IPC: H01M8/10

CPC classification number: H01M4/881 ,  H01M8/0276 ,  H01M8/028 ,  H01M8/0284 ,  H01M8/1004

Abstract: A fuel cell MEA with a border packaging structure. A catalyst coated membrane includes an anode catalyst layer, a cathode catalyst layer, and a proton exchange membrane disposed therebetween. An anode border packaging member is connected between the anode catalyst layer and an anode gas diffusion layer. A cathode border packaging member is connected between the cathode catalyst layer and a cathode gas diffusion layer and adheres to the anode border packaging member at outer edges of the catalyst coated membrane. The anode border packaging member and the cathode border packaging member respectively include two adhesive layers and a substrate layer formed therebetween. The anode border packaging member and the cathode border packaging member are respectively connected between the anode catalyst layer and the anode gas diffusion layer and between the cathode catalyst layer and the cathode gas diffusion layer by the adhesive layers.

Abstract translation: 具有边界包装结构的燃料电池MEA。 催化剂涂覆膜包括阳极催化剂层，阴极催化剂层和置于其间的质子交换膜。 阳极边界包装部件连接在阳极催化剂层和阳极气体扩散层之间。 阴极边界包装部件连接在阴极催化剂层和阴极气体扩散层之间，并且在催化剂涂覆的膜的外边缘附着到阳极边界包装部件。 阳极边界包装部件和阴极边界包装部件分别包括两个粘合剂层和在它们之间形成的基底层。 阳极边界包装部件和阴极边界包装部件分别通过粘合剂层连接在阳极催化剂层和阳极气体扩散层之间，阴极催化剂层和阴极气体扩散层之间。