公开(公告)号：US20160343886A1

公开(公告)日：2016-11-24

申请号：US15227353

申请日：2016-08-03

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch

IPC: H01L31/0232

CPC classification number: H01L31/02327 ,  H01L31/02363 ,  H01L31/0352 ,  Y02E10/50

Abstract: Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.

Abstract translation: 实施例涉及用于硅器件的掩埋结构，其可以改变光路并从而形成光阱。 光阱的实施例可以将更多的光耦合到装置的感光表面，而不是反射光或者更深地吸收光，从而可以提高效率，改进装置定时并提供本领域技术人员所理解的其它优点 。

公开(公告)号：US09293529B2

公开(公告)日：2016-03-22

申请号：US13945113

申请日：2013-07-18

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch

IPC: H01L29/00 ,  H01L29/06 ,  H01L21/762 ,  H03H3/007 ,  H03H9/24 ,  H03H9/02

CPC classification number: H01L29/0649 ,  H01L21/76202 ,  H03H3/0072 ,  H03H3/0073 ,  H03H9/2452 ,  H03H2009/02307 ,  H03H2009/02346 ,  H03H2009/02496

Abstract: A semiconductor device includes a silicon substrate layer with a decoupling region. The decoupling region of the silicon substrate layer comprises an array of lamellas laterally spaced apart from each other by cavities. Each lamella of the array of lamellas comprises at least 20% silicon dioxide.

Abstract translation: 半导体器件包括具有去耦区域的硅衬底层。 硅衬底层的解耦区域包括通过空腔彼此横向间隔开的片层阵列。 片状阵列的每个薄片包含至少20％的二氧化硅。

公开(公告)号：US09209778B2

公开(公告)日：2015-12-08

申请号：US13834486

申请日：2013-03-15

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch ,  Heiko Froehlich ,  Mirko Vogt ,  Maik Stegemann ,  Thomas Santa ,  Markus Burian

IPC: H03H9/24 ,  H03H9/02 ,  B81B3/00 ,  B81C1/00 ,  H03H3/007

CPC classification number: H03H9/2452 ,  B81B3/0078 ,  B81B2201/0271 ,  B81C1/00158 ,  B81C1/00246 ,  B81C1/00301 ,  B81C1/00396 ,  B81C2203/0145 ,  H03H3/0072 ,  H03H3/0073 ,  H03H9/02259 ,  H03H9/2463 ,  H03H2009/02291 ,  H03H2009/02307 ,  H03H2009/0233 ,  H03H2009/02496

Abstract: Embodiments relate to MEMS resonator structures and methods that enable application of a maximum available on-chip voltage. In an embodiment, a MEMS resonator comprises a connection between a ground potential and the gap electrode of the resonator. Embodiments also relate to manufacturing systems and methods that are less complex and enable production of MEMS resonators of reduced dimensions.

Abstract translation: 实施例涉及能够应用最大可用片上电压的MEMS谐振器结构和方法。 在一个实施例中，MEMS谐振器包括接地电位和谐振器的间隙电极之间的连接。 实施例还涉及不太复杂的制造系统和方法，并且能够制造尺寸减小的MEMS谐振器。

公开(公告)号：US20150021734A1

公开(公告)日：2015-01-22

申请号：US13945113

申请日：2013-07-18

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76202 ,  H03H3/0072 ,  H03H3/0073 ,  H03H9/2452 ,  H03H2009/02307 ,  H03H2009/02346 ,  H03H2009/02496

Abstract: A semiconductor device includes a silicon substrate layer with a decoupling region. The decoupling region of the silicon substrate layer comprises an array of lamellas laterally spaced apart from each other by cavities. Each lamella of the array of lamellas comprises at least 20% silicon dioxide.

Abstract translation: 半导体器件包括具有去耦区域的硅衬底层。 硅衬底层的解耦区域包括通过空腔彼此横向间隔开的片层阵列。 片状阵列的每个薄片包含至少20％的二氧化硅。

公开(公告)号：US20150001665A1

公开(公告)日：2015-01-01

申请号：US13930167

申请日：2013-06-28

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch

IPC: H01L31/0352 ,  H01L31/0232

CPC classification number: H01L31/02327 ,  H01L31/02363 ,  H01L31/0352 ,  Y02E10/50

Abstract: Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.

Abstract translation: 实施例涉及用于硅器件的掩埋结构，其可以改变光路并从而形成光阱。 光阱的实施例可以将更多的光耦合到装置的感光表面，而不是反射光或者更深地吸收光，从而可以提高效率，改进装置定时并提供本领域技术人员所理解的其它优点 。

公开(公告)号：US10354911B2

公开(公告)日：2019-07-16

申请号：US15630579

申请日：2017-06-22

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch ,  Alessia Scire ,  Steffen Bieselt

IPC: H01L21/764 ,  H01L21/762 ,  H01L27/12 ,  H01L21/324 ,  H01L29/78 ,  H01L29/06 ,  B81C1/00

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate.

公开(公告)号：US10270002B2

公开(公告)日：2019-04-23

申请号：US15196203

申请日：2016-06-29

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch

IPC: H01L31/173 ,  G01N21/552 ,  H01L33/00 ,  H01L33/20 ,  G02B6/12

Abstract: The present disclosure relates to an integrated light emitting device. The integrated light emitting device comprises a substrate of semiconductor material, a light emitting unit integrated into the semiconductor material, and at least one cavity formed into the semiconductor material between the substrate and the light emitting unit. At least portions of the at least one cavity may be formed by Silicon-On-Nothing (SON) process steps.

公开(公告)号：US10007056B2

公开(公告)日：2018-06-26

申请号：US15390178

申请日：2016-12-23

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch

IPC: H01L31/00 ,  G02B6/12 ,  G02B6/122 ,  G02B6/136 ,  H01L31/0232 ,  H01L31/054

CPC classification number: G02B6/12002 ,  G02B6/1223 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/121 ,  H01L31/02327 ,  H01L31/0547 ,  Y02E10/52

Abstract: Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.

公开(公告)号：US20180175069A1

公开(公告)日：2018-06-21

申请号：US15899437

申请日：2018-02-20

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch ,  Alessia Scire ,  Steffen Bieselt ,  Franz Hirler ,  Anton Mauder ,  Wolfgang Scholz ,  Hans-Joachim Schulze ,  Francisco Javier Santos Rodriguez

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/764 ,  H01L21/76895 ,  H01L21/823487 ,  H01L29/7397 ,  H01L29/7813 ,  H05K1/0256 ,  H05K1/0284 ,  H05K1/183 ,  H05K3/30 ,  H05K2201/10522 ,  Y10T29/4913

Abstract: According to various embodiments, an electronic device may include a carrier including at least a first region and a second region being laterally adjacent to each other; an electrically insulating structure arranged in the first region of the carrier, wherein the second region of the carrier is free of the electrically insulating structure; a first electronic component arranged in the first region of the carrier over the electrically insulating structure; a second electronic component arranged in the second region of the carrier; wherein the electrically insulating structure includes one or more hollow chambers, wherein the sidewalls of the one or more hollow chambers are covered with an electrically insulating material.

公开(公告)号：US09997595B2

公开(公告)日：2018-06-12

申请号：US15044446

申请日：2016-02-16

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762 ,  H03H3/007 ,  H03H9/24 ,  H03H9/02

CPC classification number: H01L29/0649 ,  H01L21/76202 ,  H03H3/0072 ,  H03H3/0073 ,  H03H9/2452 ,  H03H2009/02307 ,  H03H2009/02346 ,  H03H2009/02496

Abstract: A semiconductor device includes a silicon substrate layer with a decoupling region. The decoupling region of the silicon substrate layer comprises an array of lamellas laterally spaced apart from each other by cavities. Each lamella of the array of lamellas comprises at least 20% silicon dioxide.