公开(公告)号：US09646910B2

公开(公告)日：2017-05-09

申请号：US15019931

申请日：2016-02-09

Applicant: INTEL CORPORATION

Inventor： Sandeep Ahuja ,  Eric W. Buddrius ,  Roger D. Flynn ,  Rajat Agarwal

IPC: H05K7/20 ,  H05K13/00 ,  G06F1/20 ,  H01L23/36 ,  H01L23/433 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/36 ,  G06F1/20 ,  H01L21/4882 ,  H01L23/433 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H05K7/20445 ,  Y10T29/49002 ,  H01L2924/00

Abstract: In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.

公开(公告)号：US09613722B2

公开(公告)日：2017-04-04

申请号：US14497834

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： George H. Huang ,  Debaleena Das ,  Brian S. Morris ,  Rajat Agarwal

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/07

CPC classification number: G11C29/883 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/1666 ,  G06F11/2094

Abstract: An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory sparing logic to perform a first forward memory sparing operation at a first level of granularity in response to detecting a memory failure; the memory sparing logic to perform a reverse memory sparing operation in response to a determination of an improved sparing state having a second level of granularity; and the memory sparing logic to responsively perform a second forward memory sparing operation at the second level of granularity.

公开(公告)号：US20160224252A1

公开(公告)日：2016-08-04

申请号：US14609904

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： Steven R. Hutsell ,  Rajat Agarwal ,  Avinash Sodani ,  Darrell S. McGinnis

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0895 ,  G06F2212/225

Abstract: Hybrid memory architecture technologies are described. In accordance with embodiments disclosed herein, there is provided a processing device having a core and a memory controller communicably coupled to the core to receive a request to fetch data. The memory controller is communicably coupled to a hybrid memory architecture including a near memory, wherein the near memory is divided into a flat memory region and a cache memory region.

Abstract translation: 描述了混合存储器架构技术。 根据本文公开的实施例，提供了一种处理设备，其具有核心和可通信地耦合到核心的存储器控​​制器，以接收获取数据的请求。 存储器控制器可通信地耦合到包括近存储器的混合存储器架构，其中近端存储器被划分为平坦存储器区域和高速缓冲存储器区域。

公开(公告)号：US12254203B2

公开(公告)日：2025-03-18

申请号：US18145095

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  Christoph Dobraunig ,  Rajat Agarwal ,  David M. Durham ,  Santosh Ghosh ,  Karanvir Grewal ,  Krystian Matusiewicz

IPC: G06F3/06 ,  G11C7/24

Abstract: The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.

公开(公告)号：US12242342B2

公开(公告)日：2025-03-04

申请号：US17550859

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Jing Ling ,  Wei P. Chen ,  Rajat Agarwal

IPC: G06F11/10 ,  G06F11/14

Abstract: A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow without needing to send another read to the memory for the data. The read data is stored in a read data buffer (RDB) at the memory controller when the read data is received from memory. The memory controller has an error detection path from the RDB to the host and an error correction path. Read data that has no errors can be sent directly to the host. Instead of flushing the RDB in response to the error detection, the memory controller executes a retry flow, where the RDB provides the read data to the error correction path for error correction.

公开(公告)号：US20230093247A1

公开(公告)日：2023-03-23

申请号：US17481770

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Bhargavi Narayanasetty ,  Andrew Anderson ,  Anupama Kurpad ,  Evgeny V. Voevodin ,  Patrick Ndouniama ,  Sai Prashanth Muralidhara ,  Rajat Agarwal ,  Mohamed Arafa

IPC: G06F3/06

Abstract: An embodiment of an integrated circuit may comprise local memory, a plurality of per-page counters located in a non-system-addressable region of the local memory, and circuitry coupled to the local memory, the circuitry to count accesses to pages of a system-addressable memory space with the plurality of per-page counters located in the non-system-addressable region of the local memory. Other embodiments are disclosed and claimed.

公开(公告)号：US11580029B2

公开(公告)日：2023-02-14

申请号：US17223113

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02

Abstract: A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.

公开(公告)号：US11196565B2

公开(公告)日：2021-12-07

申请号：US16689575

申请日：2019-11-20

Applicant: INTEL CORPORATION

Inventor： David M. Durham ,  Rajat Agarwal ,  Siddhartha Chhabra ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Ioannis T. Schoinas

IPC: H04L9/32 ,  G06F3/06 ,  G06F11/10 ,  G06F12/14 ,  G06F12/0886 ,  G06F21/78 ,  H04L9/06 ,  H04L9/08 ,  H04L9/30 ,  G06F21/14 ,  G11C29/52 ,  G06F21/79 ,  G11C29/44

Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.

公开(公告)号：US11132298B2

公开(公告)日：2021-09-28

申请号：US16052581

申请日：2018-08-01

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J Hinton

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0893 ,  G06F12/02 ,  G11C7/10 ,  G06F12/06 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0806 ,  G06F12/0888 ,  G11C14/00 ,  G11C13/00

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

公开(公告)号：US11088846B2

公开(公告)日：2021-08-10

申请号：US16368810

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Rajat Agarwal ,  David M. Durham

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/00 ,  H04L9/08 ,  H04L9/06 ,  H04L9/16

Abstract: In one example a computer implemented method comprises encrypting data to be stored in a protected region of a memory using a message authentication code (MAC) having a first value determined using a first key during a first period of time, generating a replay integrity tree structure comprising security metadata for the data stored in the protected region of the memory using the first value of the MAC, and at the end of the first period of time, re-keying the MAC to have a second value determined using a second key at the end of the first period of time, decrypting the data stored in the protected region using the first value for the MAC, re-encrypting the data stored in the protected region using the second value for the MAC, and updating the replay integrity tree using the second value for the MAC. Other examples may be described.