公开(公告)号：US10705673B2

公开(公告)日：2020-07-07

申请号：US15721768

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Glen J. Anderson ,  Giuseppe Raffa ,  Sangita Sharma ,  Carl S. Marshall ,  Meng Shi ,  Selvakumar Panneer

IPC: G06F3/0481 ,  G06F16/23 ,  G06F3/01

Abstract: Systems, apparatuses and methods for technology that provides smart work spaces in ubiquitous computing environments. The technology may determine a task to be performed in a smart work space and perform task modeling, wherein the task modeling includes determining one or more user interfaces involved with the task. One or more placements may be determined for the one or more user interfaces based on one or more ergonomic conditions, an incidence of an interaction, and a length of time of interaction. The technology may position the one or more user interfaces into the smart work space in accordance with the determined one or more placements.

公开(公告)号：US20170140498A1

公开(公告)日：2017-05-18

申请号：US15354532

申请日：2016-11-17

Applicant: Intel Corporation

Inventor： Sameer Kp ,  Selvakumar Panneer ,  Susanta Bhattacharjee ,  Mrinalini Attaluri

IPC: G06T1/20 ,  G09G5/36 ,  G09G5/39

CPC classification number: G09G5/39 ,  G06T1/20 ,  G06T1/60 ,  G09G5/363 ,  G09G2360/12 ,  G09G2360/18

Abstract: Methods, apparatus, and articles of manufacture to provide extended graphics processing capabilities are disclosed. A disclosed example method involves sending a display panel parameter to a shared library module. The display panel parameter is sent by a programmable driver interface in communication between the shared library module and a graphics hardware device driver. The shared library module includes a first graphics processing capability. The graphics hardware device driver includes a second graphics processing capability different from the first graphics processing capability. The example method also involves performing a render operation via the programmable driver interface on a frame buffer based on the first graphics processing capability. The first graphics processing capability is received at the programmable driver interface from the shared library module based on the display panel parameter. The frame buffer is output to a display.

公开(公告)号：US09530386B2

公开(公告)日：2016-12-27

申请号：US14227908

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Sameer Kp ,  Selvakumar Panneer ,  Susanta Bhattacharjee ,  Mrinalini Attaluri

IPC: G06F13/14 ,  G06T1/00 ,  G06F15/00 ,  G09G5/39 ,  G06T1/20

CPC classification number: G09G5/39 ,  G06T1/20 ,  G06T1/60 ,  G09G5/363 ,  G09G2360/12 ,  G09G2360/18

Abstract: Methods, apparatus, and articles of manufacture to provide extended graphics processing capabilities are disclosed. A disclosed example method involves sending a display panel parameter to a shared library module. The display panel parameter is sent by a programmable driver interface in communication between the shared library module and a graphics hardware device driver. The shared library module includes a first graphics processing capability. The graphics hardware device driver includes a second graphics processing capability different from the first graphics processing capability. The example method also involves performing a render operation via the programmable driver interface on a frame buffer based on the first graphics processing capability. The first graphics processing capability is received at the programmable driver interface from the shared library module based on the display panel parameter. The frame buffer is output to a display.

Abstract translation: 公开了提供扩展图形处理能力的方法，装置和制品。 公开的示例性方法涉及将显示面板参数发送到共享库模块。 显示面板参数由共享库模块和图形硬件设备驱动程序之间通信的可编程驱动程序接口发送。 共享库模块包括第一图形处理能力。 图形硬件设备驱动器包括与第一图形处理能力不同的第二图形处理能力。 该示例方法还涉及基于第一图形处理能力，经由帧缓冲器上的可编程驱动器接口执行渲染操作。 基于显示面板参数，在共享库模块的可编程驱动器接口处接收第一图形处理能力。 帧缓冲区被输出到显示器。

公开(公告)号：US12243192B2

公开(公告)日：2025-03-04

申请号：US17354186

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Satyam Srivastava ,  Saurabh Tangri ,  Rajeev Nalawadi ,  Carl S. Marshall ,  Selvakumar Panneer

IPC: G06T5/70 ,  G06N3/045 ,  G06N3/08 ,  G06T3/40 ,  G06T5/50

Abstract: An apparatus to facilitate video motion smoothing is disclosed. The apparatus comprises one or more processors including a graphics processor, the one or more processors including circuitry configured to receive a video stream, decode the video stream to generate a motion vector map and a plurality of video image frames, analyze the motion vector map to detect a plurality of candidate frames, wherein the plurality of candidate frames comprise a period of discontinuous motion in the plurality of video image frames and the plurality of candidate frames are determined based on a classification generated via a convolutional neural network (CNN), generate, via a generative adversarial network (GAN), one or more synthetic frames based on the plurality of candidate frames, insert the one or more synthetic frames between the plurality of candidate frames to generate up-sampled video frames and transmit the up-sampled video frames for display.

公开(公告)号：US12243157B2

公开(公告)日：2025-03-04

申请号：US18610369

申请日：2024-03-20

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Carl S. Marshall ,  Ravishankar Iyer ,  Zack Waters

IPC: G06T15/80 ,  G06N3/08 ,  G06T15/00 ,  G06T15/10

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

公开(公告)号：US12164973B2

公开(公告)日：2024-12-10

申请号：US18511296

申请日：2023-11-16

Applicant: Intel Corporation

Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

公开(公告)号：US20240345990A1

公开(公告)日：2024-10-17

申请号：US18626775

申请日：2024-04-04

Applicant: Intel Corporation

Inventor： Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Varghese George ,  Ben Ashbaugh ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek Appu ,  Nicolas Galoppo Von Borries ,  Altug Koker ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Nilay Mistry ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Ankur Shah ,  Saurabh Tangri

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

公开(公告)号：US20240312113A1

公开(公告)日：2024-09-19

申请号：US18607243

申请日：2024-03-15

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  John H. Feit

IPC: G06T15/04 ,  G06T3/4053 ,  G06T7/20 ,  G06T15/50

CPC classification number: G06T15/04 ,  G06T3/4053 ,  G06T7/20 ,  G06T15/506

Abstract: Described herein are techniques to render frame data in UV space and process the UV space data via a machine learning model. One embodiment provides an apparatus including a parallel processor having first circuitry configured to execute operations associated with a three-dimensional (3D) application programming interface (API) to render scene data for a frame in a UV coordinate space, second circuitry configured to execute instructions to perform a matrix multiply accumulate operation associated with a machine learning model that is trained to process the scene data in the UV coordinate space to generate processed scene data in the UV coordinate space, and third circuitry to rasterize the processed scene data in the UV coordinate space into a screen space representation of the scene data.

公开(公告)号：US20240312028A1

公开(公告)日：2024-09-19

申请号：US18478271

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Lorenzo Tessari

IPC: G06T7/246 ,  G06T3/00 ,  G06T15/80

CPC classification number: G06T7/251 ,  G06T3/18 ,  G06T7/248 ,  G06T15/80

Abstract: Described herein, in one embodiment, is computer-implemented method of estimating dense optical flow using primitive ID data comprising generating a primitive ID buffer (e.g., triangle ID buffer) for a frame during rendering, rendering the frame with a unique color for each primitive ID, providing a rendered primitive ID buffer for the current and previous frame along with a confidence buffer and sparse optical flow between frames to a machine learning model, and generating an estimated dense optical flow via the machine learning model based on the input.

公开(公告)号：US12079155B2

公开(公告)日：2024-09-03

申请号：US17428216

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Selvakumar Panneer ,  Saurabh Tangri ,  Ben Ashbaugh ,  Scott Janus ,  Abhishek Appu ,  Varghese George ,  Ravishankar Iyer ,  Nilesh Jain ,  Pattabhiraman K ,  Altug Koker ,  Mike MacPherson ,  Josh Mastronarde ,  Elmoustapha Ould-Ahmed-Vall ,  Jayakrishna P. S ,  Eric Samson

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.