公开(公告)号：US20230087624A1

公开(公告)日：2023-03-23

申请号：US17483795

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  I-Cheng TUNG ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Arnab SEN GUPTA

IPC: H01L49/02

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to increasing the capacitance density of MIM capacitors on dies or within packages. In particular, a MIM stack is disclosed that has multiple insulator layers between the metal, in order to increase the dielectric constant of the MIM stack. In particular, the first dielectric layer may include strontium, titanium, and oxygen and may be physically coupled with a second dielectric layer that may include barium, strontium, titanium, and oxygen. Other embodiments may be described and/or claimed.

公开(公告)号：US20220415894A1

公开(公告)日：2022-12-29

申请号：US17894968

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20220199799A1

公开(公告)日：2022-06-23

申请号：US17131706

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Chelsey DOROW ,  Carl NAYLOR ,  Kirby MAXEY ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Ashish Verma PENUMATCHA ,  Chia-Ching LIN ,  Shriram SHIVARAMAN ,  Sudarat LEE

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

Abstract: Thin film transistors having boron nitride integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first gate stack above a substrate. A 2D channel material layer is above the first gate stack. A second gate stack is above the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack and in contact with the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack and in contact with the 2D channel material layer. A hexagonal boron nitride (hBN) layer is included between the first gate stack and the 2D channel material layer, between the second gate stack and the 2D channel material layer, or both.

公开(公告)号：US20210391478A1

公开(公告)日：2021-12-16

申请号：US16902069

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Carl NAYLOR ,  Ashish Verma PENUMATCHA ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/24

Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.

公开(公告)号：US20210167182A1

公开(公告)日：2021-06-03

申请号：US16700757

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Ashish Verma PENUMATCHA ,  Sou-Chi CHANG ,  Devin MERRILL ,  I-Cheng TUNG ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Shriram SHIVARAMAN ,  Eric Charles MATTSON

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20210111179A1

公开(公告)日：2021-04-15

申请号：US16599422

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Nazila HARATIPOUR ,  Uygar E. AVCI

IPC: H01L27/11514 ,  H01L49/02 ,  H01L27/11507 ,  G11C11/22 ,  H01L27/11504

Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.

公开(公告)号：US20190027211A1

公开(公告)日：2019-01-24

申请号：US16078582

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: G11C11/412 ,  G11C11/419 ,  G11C8/16 ,  H01L27/11

CPC classification number: G11C11/412 ,  G11C8/16 ,  G11C11/223 ,  G11C11/419 ,  H01L27/11

Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

公开(公告)号：US20180301533A1

公开(公告)日：2018-10-18

申请号：US15569269

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Uygar E. AVCI ,  Ian A. YOUNG

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267 ,  H01L29/205

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/78

Abstract: Fermi filter field effect transistors having a Fermi filter between a source and a source contact, systems incorporating such transistors, and methods for forming them are discussed. Such transistors may include a channel between a source and a drain both having a first polarity and a Fermi filter between the source and a source contact such that the Fermi filter has a second polarity complementary to the first polarity.

公开(公告)号：US20160056278A1

公开(公告)日：2016-02-25

申请号：US14779943

申请日：2013-06-27

Applicant: INTEL CORPORATION

Inventor： Uygar E. AVCI ,  Raseong KIM ,  Ian A. YOUNG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66977 ,  H01L29/7391

Abstract: Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions.

Abstract translation: 描述了具有未掺杂漏极覆盖环绕区域的隧道场效应晶体管（TFET）。 例如，隧道场效应晶体管（TFET）包括形成在衬底上方的均质有源区。 同质结有源区包括掺杂源极区，未掺杂沟道区，缠绕区和掺杂漏极区。 在未掺杂的沟道区域，源极和缠绕区域之间形成栅电极和栅介质层。

公开(公告)号：US20240186416A1

公开(公告)日：2024-06-06

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L21/02568 ,  H01L21/0262

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.