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    Interconnect integration scheme with fully self-aligned vias
    51.
    发明授权
    Interconnect integration scheme with fully self-aligned vias 有权

    公开(公告)号：US11264276B2

    公开(公告)日：2022-03-01

    申请号：US16659734

    申请日：2019-10-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Shyng-Tsong Chen ,  Terry A. Spooner

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

    Abstract: A method is presented for forming self-aligned vias by employing a top level line pattern. The method includes forming first conductive lines within a first dielectric material, recessing one conductive line of the conductive lines to define a first opening, filling the first opening with a second dielectric material, and forming a sacrificial block perpendicular to and in direct contact with a non-recessed first conductive line. The method further includes forming a single via directly underneath the sacrificial block by recessing the non-recessed first conductive line, removing the sacrificial block to define a second opening, and filling the second opening with a conductive material to define a second conductive line such that the single via aligns to both the non-recessed first conductive line and the second conductive line.

    Interconnect structures including self aligned vias
    52.
    发明授权
    Interconnect structures including self aligned vias 有权

    公开(公告)号：US11227792B2

    公开(公告)日：2022-01-18

    申请号：US16576712

    申请日：2019-09-19

    Applicant: International Business Machines Corporation

    Inventor： Chih-Chao Yang ,  Terry A. Spooner ,  Koichi Motoyama ,  Shyng-Tsong Chen

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

    Abstract: Back end of line metallization structures and methods for fabricating self-aligned vias. The structures generally include a first interconnect structure disposed above a substrate. The first interconnect structure includes a metal line formed in a first interlayer dielectric. A second interconnect structure overlies the first interconnect structure. The second interconnect structure includes a second cap layer on the first interlayer dielectric, a second interlayer dielectric thereon, and at least one self-aligned via in the second interlayer dielectric conductively coupled to at least a portion of the metal line of the first interconnect structure, wherein any misalignment of the at least one self-aligned via results in the at least one self-aligned via landing on both the metal line of the first interconnect structure and the second cap layer. The second cap layer is an insulating material.

    INTERCONNECT STRUCTURES INCLUDING SELF ALIGNED VIAS
    53.
    发明申请
    INTERCONNECT STRUCTURES INCLUDING SELF ALIGNED VIAS 有权

    公开(公告)号：US20210090942A1

    公开(公告)日：2021-03-25

    申请号：US16576712

    申请日：2019-09-19

    Applicant: International Business Machines Corporation

    Inventor： Chih-Chao Yang ,  Terry A. Spooner ,  Koichi Motoyama ,  Shyng-Tsong Chen

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

    Abstract: Back end of line metallization structures and methods for fabricating self-aligned vias. The structures generally include a first interconnect structure disposed above a substrate. The first interconnect structure includes a metal line formed in a first interlayer dielectric. A second interconnect structure overlies the first interconnect structure. The second interconnect structure includes a second cap layer on the first interlayer dielectric, a second interlayer dielectric thereon, and at least one self-aligned via in the second interlayer dielectric conductively coupled to at least a portion of the metal line of the first interconnect structure, wherein any misalignment of the at least one self-aligned via results in the at least one self-aligned via landing on both the metal line of the first interconnect structure and the second cap layer. The second cap layer is an insulating material.

    Low resistance contact for transistors
    54.
    发明授权
    Low resistance contact for transistors 有权

    公开(公告)号：US10923575B2

    公开(公告)日：2021-02-16

    申请号：US16546351

    申请日：2019-08-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Lawrence A. Clevenger ,  Junli Wang ,  Kirk D. Peterson ,  Baozhen Li ,  Terry A. Spooner ,  John E. Sheets, II

    IPC: H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

    Abstract: According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact.

    Low resistance contact for transistors
    55.
    发明授权
    Low resistance contact for transistors 有权

    公开(公告)号：US10468491B1

    公开(公告)日：2019-11-05

    申请号：US16026337

    申请日：2018-07-03

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Lawrence A. Clevenger ,  Junli Wang ,  Kirk D. Peterson ,  Baozhen Li ,  Terry A. Spooner ,  John E. Sheets, II

    IPC: H01L21/768 ,  H01L29/45 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

    Abstract: According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact.

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