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公开(公告)号：US10228755B2
公开(公告)日：2019-03-12
申请号：US15281806
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Doron Rajwan , Efraim Rotem , Avinash N. Ananthakrishnan , Ankush Varma , Assaf Ganor , Nir Rosenzweig , David M. Pawlowski , Arik Gihon , Nadav Shulman
IPC: G06F1/28 , G06F1/32 , G06F1/3296
Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.
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公开(公告)号：US20190011975A1
公开(公告)日：2019-01-10
申请号：US16044994
申请日：2018-07-25
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah
IPC: G06F1/32 , G06F12/0846 , G06F1/28 , G06F12/0802 , G06F12/084 , G06F12/0864
Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
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公开(公告)号：US09618997B2
公开(公告)日：2017-04-11
申请号：US14565723
申请日：2014-12-10
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Ryan Wells , Nadav Shulman
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/3885 , Y02D10/126 , Y02D10/152 , Y02D10/171
Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
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公开(公告)号：US20160011975A1
公开(公告)日：2016-01-14
申请号：US14840639
申请日：2015-08-31
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah
CPC classification number: G06F1/3275 , G06F1/28 , G06F1/3287 , G06F12/0802 , G06F12/084 , G06F12/0848 , G06F12/0864 , G06F2212/1028 , G06F2212/282 , G06F2212/502 , G06F2212/621 , Y02D10/13
Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
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55.发明授权公开(公告)号：US09081557B2
公开(公告)日：2015-07-14
申请号：US14143939
申请日：2013-12-30
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Nadav Shulman
CPC classification number: G06F1/26 , G06F1/3243 , G06F9/5094 , Y02D10/152
Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于当前时间间隔确定多域处理器的功率预算的方法，确定要分配给处理器的第一和第二域的功率预算的一部分，以及控制频率 基于所分配的部分的域。 这样的确定和分配可以在处理器的运行期间动态地执行。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US20150095673A1
公开(公告)日：2015-04-02
申请号：US14565723
申请日：2014-12-10
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Eliezer Wiessmann , Ryan Wells , Nadav Shulman
IPC: G06F1/32
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/3885 , Y02D10/126 , Y02D10/152 , Y02D10/171
Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有功率控制器以控制处理器工作频率的多核处理器。 更具体地，功率控制器可以将处理器的最大工作频率限制在小于配置的最大工作频率，以便能够减少响应于电力状态事件而发生的频率转换的数量，从而避免在处理这些操作时所执行的操作的开销 转换 描述和要求保护其他实施例。
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公开(公告)号：US11698812B2
公开(公告)日：2023-07-11
申请号：US16554940
申请日：2019-08-29
Applicant: Intel Corporation
CPC classification number: G06F9/4893 , G06F1/08 , G06F1/10 , G06F1/3296 , G06F1/324
Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.
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公开(公告)号：US20230004201A1
公开(公告)日：2023-01-05
申请号：US17867187
申请日：2022-07-18
Applicant: Intel Corporation
Inventor： Muhammad Abozaed , Eugene Gorbatov , Gaurav Khanna , Avinash N. Ananthakrishnan
IPC: G06F1/20 , G06F9/48 , G06F1/3206
Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.
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公开(公告)号：US11119555B2
公开(公告)日：2021-09-14
申请号：US16544010
申请日：2019-08-19
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Jeremy J. Shrall , Anupama Suryanarayanan , Ameya Ambardekar , Craig Topper , Eric R. Heit , Joseph M. Alberts
IPC: G06F1/28 , G06F12/0897 , G06F12/0875 , G06F12/084 , G06F1/30 , G06F1/3296
Abstract: In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.
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公开(公告)号：US20200042065A1
公开(公告)日：2020-02-06
申请号：US16544010
申请日：2019-08-19
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Jeremy J. Shrall , Anupama Suryanarayanan , Ameya Ambardekar , Craig Topper , Eric R. Heit , Joseph M. Alberts
IPC: G06F1/28 , G06F12/0897 , G06F12/0875 , G06F12/084 , G06F1/30 , G06F1/3296
Abstract: In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.
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