公开(公告)号：US20190139592A1

公开(公告)日：2019-05-09

申请号：US16177284

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Ge Chang

IPC: G11C11/4074 ,  G11C11/408 ,  G11C7/10 ,  G11C8/06 ,  G06F3/06 ,  G06F13/16

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

公开(公告)号：US20190042500A1

公开(公告)日：2019-02-07

申请号：US16017515

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Bill NALE ,  Chong J. ZHAO ,  James A. McCALL ,  George VERGIS

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.

公开(公告)号：US20190042497A1

公开(公告)日：2019-02-07

申请号：US15970639

申请日：2018-05-03

Applicant: Intel Corporation

Inventor： Rajesh BHASKAR ,  Kenneth FOUST ,  George VERGIS

IPC: G06F13/16 ,  G06F13/40 ,  G06F1/18 ,  G06F13/42 ,  H01R12/72 ,  G11C5/02

Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

公开(公告)号：US20180061478A1

公开(公告)日：2018-03-01

申请号：US15282757

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： George VERGIS ,  Kuljit S. BAINS

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4076

Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.

公开(公告)号：US20180004592A1

公开(公告)日：2018-01-04

申请号：US15650479

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  George VERGIS

IPC: G06F11/10 ,  G11C29/44 ,  G11C7/10 ,  G11C29/42 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F11/10 ,  G06F11/108 ,  G11C5/04 ,  G11C7/1063 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

公开(公告)号：US20250124994A1

公开(公告)日：2025-04-17

申请号：US18986494

申请日：2024-12-18

Applicant: Intel Corporation

Inventor： Dat T. LE ,  George VERGIS ,  Alejandro LARIOS

IPC: G11C29/02 ,  G11C29/14 ,  G11C29/44

Abstract: Methods and apparatus for DDR5 DIMM power fail monitor to prevent I/O reverse-bias current. An apparatus is configured to be implemented in a host system including a processor having an integrated memory controller (iMC) coupled to one or more DIMMs having an onboard Power Management Integrated Circuit (PMIC). The apparatus includes circuitry to monitor an operating state for a host voltage regulator (VR) providing input power to the processor and monitor an operating state of the PMIC for each of the one or more DIMMs. In response to detecting a fault condition of the host VR or a PMIC for a DIMM, the apparatus prevents reverse bias voltage in circuitry in at least one of the iMC and the one or more DIMMs. The apparatus may implement a finite state machine (FSN) having a plurality of defined states including a fault state used to indicate detection of the fault condition.

公开(公告)号：US20250117343A1

公开(公告)日：2025-04-10

申请号：US18990908

申请日：2024-12-20

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  George VERGIS

IPC: G06F13/16

Abstract: A system includes a memory die stack that provides sensing information via proxy. The memory die stack includes at least a first memory die with a sensor that generates sensing data for the first memory die and a second memory die with a sensor that generates sensing data for the second memory die. The proxy is a logic device that aggregates and sends the sensing data for both memory dies over a management communication bus.

公开(公告)号：US20240320347A1

公开(公告)日：2024-09-26

申请号：US18679060

申请日：2024-05-30

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  George VERGIS

IPC: G06F21/60

CPC classification number: G06F21/602 ,  G06F21/606

Abstract: A memory subsystem allows the memory controller and the memory to create a trusted communication channel based on a certificate exchange. The memory and memory controller have a key storage to store the certificates. The memory controller can be restricted to only be enabled to access a system data storage array after the trusted communication channel is established.

公开(公告)号：US20240134982A1

公开(公告)日：2024-04-25

申请号：US18401428

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： George VERGIS ,  Shigeki TOMISHIMA

IPC: G06F21/56 ,  G06F21/55

CPC classification number: G06F21/566 ,  G06F21/554 ,  G06F2221/034

Abstract: Examples include techniques for a memory module per row activate counter. The techniques include detecting a row hammer or row disturb condition for a row address at a volatile memory device if an activate count to the row address matches a threshold count. The activate count is maintained by a controller for the memory module. Detection of the row hammer or row disturb condition can cause refresh management actions to mitigate the row hammer or row disturb condition.

公开(公告)号：US20230273654A1

公开(公告)日：2023-08-31

申请号：US18195072

申请日：2023-05-09

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  Phil GENG

IPC: G06F1/18

CPC classification number: G06F1/181 ,  H05K1/14

Abstract: A standalone top cover retention mechanism can attach to the top of an array of tall (e.g., 2U) DIMMs to provide structural support. In one example, the DIMM cover is attached to two or more DIMMs without attaching to the chassis. The DIMM cover can mitigate shock and vibration related failures at the DIMM level without significant interference with platform thermal mechanical solutions.