-
51.发明授权公开(公告)号：US10251011B2
公开(公告)日：2019-04-02
申请号：US15494742
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Joydeep Ray , Travis T. Schluessler , Prasoonkumar Surti , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , James M. Holland , Jeffery S. Boles , Jonathan Kennedy , Louis Feng , Atsuo Kuwahara , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
-
公开(公告)号：US10152822B2
公开(公告)日：2018-12-11
申请号：US15477019
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer KP , Jonathan Kennedy , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Tomer Bar-On , Carsten Benthin , Adam T. Lake , Vasanth Ranganathan , Abhishek R. Appu
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
-
公开(公告)号：US20180293760A1
公开(公告)日：2018-10-11
申请号：US15483701
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
CPC classification number: G06T11/001 , G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/52
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
-
公开(公告)号：US20250117060A1
公开(公告)日：2025-04-10
申请号：US18883328
申请日：2024-09-12
Applicant: INTEL CORPORATION
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
IPC: G06F1/26 , G06F12/0875
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US12050502B2
公开(公告)日：2024-07-30
申请号：US18327131
申请日：2023-06-01
Applicant: Intel Corporation
Inventor： Mohammed Tameem , Altug Koker , Kiran C. Veernapu , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Travis T. Schluessler , Jonathan Kennedy
IPC: G06F1/3234 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F13/16 , G06F13/40
CPC classification number: G06F1/3253 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F13/1678 , G06F13/4022
Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.
-
Patent Agency Ranking
56.发明公开公开(公告)号：US20240163631A1
公开(公告)日：2024-05-16
申请号：US18517862
申请日：2023-11-22
Applicant: Intel Corporation
Inventor： Joydeep Ray , Travis T. Schluessler , Prasoonkumar Surti , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , James M. Holland , Jeffery S. Boles , Jonathan Kennedy , Louis Feng , Atsuo Kuwahara , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
CPC classification number: H04S7/303 , G06F3/016 , G06T1/20 , G06T15/06 , G09B21/003 , G09B21/006 , G09B21/008 , H04R1/406 , H04R3/005 , H04S2400/11 , H04S2420/01
Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
-
公开(公告)号：US20240161356A1
公开(公告)日：2024-05-16
申请号：US18517318
申请日：2023-11-22
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer KP , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
CPC classification number: G06T11/001 , G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/52
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
-
公开(公告)号：US20230393642A1
公开(公告)日：2023-12-07
申请号：US18327131
申请日：2023-06-01
Applicant: Intel Corporation
Inventor： Mohammed Tameem , Altug Koker , Kiran C. Veernapu , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Travis T. Schluessler , Jonathan Kennedy
IPC: G06F1/3234 , G06F13/16 , G06F13/40 , G06F1/3296 , G06F1/324 , G06F1/3206 , G06F1/3287
CPC classification number: G06F1/3253 , G06F13/1678 , G06F13/4022 , G06F1/3296 , G06F1/324 , G06F1/3206 , G06F1/3287
Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.
-
公开(公告)号：US11733758B2
公开(公告)日：2023-08-22
申请号：US17411878
申请日：2021-08-25
Applicant: INTEL CORPORATION
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
IPC: G09G3/00 , G06F1/3209 , H04W52/02 , G06F1/324 , G06F1/3203 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F3/01 , G06F11/07 , G06F11/30 , H04M1/72448
CPC classification number: G06F1/3209 , G06F1/3203 , G06F1/324 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F3/01 , G06F11/0781 , G06F11/3062 , H04W52/0258 , H04M1/72448 , Y02D10/00 , Y02D30/70
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
-
60.发明授权公开(公告)号：US11537403B2
公开(公告)日：2022-12-27
申请号：US17213453
申请日：2021-03-26
Applicant: Intel Corporation
Inventor： Subramaniam M. Maiyuran , Guei-Yuan Lueh , Supratim Pal , Gang Chen , Ananda V. Kommaraju , Joy Chandra , Altug Koker , Prasoonkumar Surti , David Puffer , Hong Bin Liao , Joydeep Ray , Abhishek R. Appu , Ankur N. Shah , Travis T. Schluessler , Jonathan Kennedy , Devan Burke
Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.
-
-
-
-
-
-
-
-
-
Search Results
78
records
(took 0.022 seconds)
