公开(公告)号：US08363445B2

公开(公告)日：2013-01-29

申请号：US13283267

申请日：2011-10-27

申请人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

发明人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/115

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 可移位阈值电压晶体管具有漏极和栅极短路在一起。 编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。 在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。 编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

公开(公告)号：US20120299187A1

公开(公告)日：2012-11-29

申请号：US13166562

申请日：2011-06-22

申请人： Kent Charles OERTLE ,  Wei Xia ,  Edward Law

发明人： Kent Charles OERTLE ,  Wei Xia ,  Edward Law

IPC分类号： H01L23/485 ,  H01L21/50

CPC分类号： H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/036 ,  H01L2224/03831 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/05552

摘要： Embodiments of an aluminum pad thinning in bond pad for fine pitch ultra-thick aluminum pad structures are provided herein. Embodiments include a conductive structure formed on a substrate. A first passivation layer is formed over the substrate and the conductive structure, the first passivation layer having an opening formed over the conductive structure. An ultra-thick conductive structure having a thinned trench region formed over the opening of the first passivation layer. The ultra-thick conductive structure is in contact with the conductive structure. A second passivation layer formed over the first passivation region and the ultra-thick conductive structure. The second passivation layer having an opening formed over the thinned trench region of the ultra-thick conductive structure.

摘要翻译： 本文提供了用于细间距超厚铝垫结构的接合垫中的铝垫减薄的实施例。 实施例包括形成在基板上的导电结构。 第一钝化层形成在衬底和导电结构之上，第一钝化层具有形成在导电结构上的开口。 一种超厚导电结构，其具有形成在第一钝化层的开口上的减薄沟槽区。 超厚导电结构与导电结构接触。 形成在第一钝化区域和超厚导电结构上的第二钝化层。 第二钝化层具有形成在超厚导电结构的减薄的沟槽区域上的开口。

公开(公告)号：US20120217613A1

公开(公告)日：2012-08-30

申请号：US13466986

申请日：2012-05-08

申请人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

发明人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

摘要翻译： 根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属 熔丝形成在栅极金属段的一部分中。 该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。 该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。

公开(公告)号：US20120097896A1

公开(公告)日：2012-04-26

申请号：US13319272

申请日：2010-05-05

申请人： Zhiguo Xiao ,  Xifeng Wang ,  Wei Xia ,  Shiyun Sang ,  Jianxiong Liu ,  Hongwei Zhang

发明人： Zhiguo Xiao ,  Xifeng Wang ,  Wei Xia ,  Shiyun Sang ,  Jianxiong Liu ,  Hongwei Zhang

IPC分类号： C09K11/79 ,  C09K11/85

CPC分类号： C09K11/7792 ,  Y02B20/181

摘要： The present invention provides blue-green silicate luminescent materials, which are rare earth activated alkaline-earth metals silicates having a formula of Ba1-bMbSi2O(5-a/2)Da:Eux, Lny, wherein M is one or two elements selected from the group consisting of Mg, Ca and Sr; D is one or two ions selected from the group consisting of Cl− and F−; Ln is an ion selected from Ce, Er, Pr or Mn; a, b, x, and y are molar coefficients and within following ranges: 0≦a

摘要翻译： 本发明提供蓝色 - 绿色硅酸盐发光材料，它们是具有式Ba1-bMbSi2O（5-a / 2）Da:Eux，Lny的稀土活化的碱土金属硅酸盐，其中M是选自以下的一种或两种元素： 由Mg，Ca和Sr组成的组; D是选自Cl-和F-的一种或两种离子; Ln是选自Ce，Er，Pr或Mn的离子; a，b，x和y是摩尔系数，并在以下范围内：0＆nlE; a <2,0＆nlE; b <0.5,0

公开(公告)号：US20110274070A1

公开(公告)日：2011-11-10

申请号：US13143195

申请日：2009-11-17

申请人： Wei Xia ,  Yanfeng Guan ,  Zhaohua Lu ,  Dengkui Zhu ,  Ying Liu ,  Ding Ning

发明人： Wei Xia ,  Yanfeng Guan ,  Zhaohua Lu ,  Dengkui Zhu ,  Ying Liu ,  Ding Ning

IPC分类号： H04W72/04

CPC分类号： H04W72/005 ,  H04W72/04 ,  H04W72/121

摘要： The present invention discloses a group resource allocation method, which comprises the following steps that: a user resource management device groups user-side equipments according to the service type or the modulation and coding scheme of the user-side equipments; and the user resource management device performs an initialization description and/or an update and maintenance description for each group via a group message, describes the resource allocation information of the user-side equipments in each group via the group message to realize a group resource allocation. Through the technical solution above, the present invention lowers the description overhead of a group resource allocation.

摘要翻译： 本发明公开了一种群资源分配方法，包括以下步骤：用户资源管理设备根据用户侧设备的业务类型或调制编码方式对用户侧设备进行分组; 用户资源管理装置经由组消息对每个组进行初始化描述和/或更新维护描述，经由组消息描述每个组中的用户侧设备的资源分配信息，以实现组资源分配 。 通过上述技术方案，本发明降低了组资源分配的描述开销。

公开(公告)号：US20110240123A1

公开(公告)日：2011-10-06

申请号：US12751516

申请日：2010-03-31

申请人： Hao LIN ,  Wei Xia ,  Hsiang Ning Wu ,  Ching Wan TANG

发明人： Hao LIN ,  Wei Xia ,  Hsiang Ning Wu ,  Ching Wan TANG

IPC分类号： H01L31/00

CPC分类号： H01L31/0392 ,  H01L31/0296 ,  H01L31/03925 ,  H01L31/073 ,  H01L31/1836 ,  Y02E10/543

摘要： A photovoltaic cell comprising a metal oxide back buffer layer. Improved n-CdS/p-CdTe heterojunction photovoltaic cells comprising a metal oxide buffer layer for making low-resistance electrical contact to the p-type CdTe layer. The back buffer layer comprises metal oxides having a high work function.

摘要翻译： 一种包含金属氧化物背缓冲层的光伏电池。 包括用于与p型CdTe层进行低电阻电接触的金属氧化物缓冲层的改进的n-CdS / p-CdTe异质结光伏电池。 后缓冲层包括具有高功函数的金属氧化物。

公开(公告)号：US20110108903A1

公开(公告)日：2011-05-12

申请号：US12590370

申请日：2009-11-06

申请人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

发明人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11526 ,  H01L27/11546

摘要： According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

摘要翻译： 根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分 电介质层。 浮栅包括金属一层的一部分，电介质一层包括第一高k电介质材料。 控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

公开(公告)号：US20110089490A1

公开(公告)日：2011-04-21

申请号：US12589357

申请日：2009-10-21

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US20110037144A1

公开(公告)日：2011-02-17

申请号：US12583016

申请日：2009-08-13

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L28/90 ,  H01L29/94 ,  H01L29/945

摘要： According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.

摘要翻译： 根据示例性实施例，在晶片中制造去耦复合电容器的方法包括覆盖在衬底上的电介质区域包括在电介质区域和衬底中形成贯通晶片通孔。 贯通晶片通孔包括覆盖贯通晶片通孔开口的侧壁和底部的贯通晶片通孔绝缘体，以及通过绝缘体覆盖贯通晶片的贯通晶片通孔导体。 该方法还包括使衬底变薄，形成衬底背面绝缘体，在衬底背面绝缘体中形成开口以通过导体暴露通过晶片，以及通过导体在透晶片上形成背面导体，使得衬底背侧导体 延伸到衬底背面绝缘体上，从而形成去耦复合电容器。 衬底形成第一去耦合复合电容器电极，并且通过晶片通孔导体和衬底背侧导体形成第二去耦复合电容器电极。

公开(公告)号：US20100284210A1

公开(公告)日：2010-11-11

申请号：US12387573

申请日：2009-05-05

申请人： Henry Kuo-Shun Chen ,  Xiangdong Chen ,  Wei Xia

发明人： Henry Kuo-Shun Chen ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/00

CPC分类号： G11C17/16

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The cell transistor has a source, a gate, and a body shorted together. A programming operation causes a punchthrough to occur between the source and a drain of the cell transistor in response to a programming voltage on the bitline and the wordline. A channel length of the cell transistor is substantially less than a channel length of the access transistor. In one embodiment, the access transistor is an NFET while the cell transistor is a PFET. In another embodiment, the access transistor is an NFET and the cell transistor is also an NFET. Various embodiments result in a reduction of the required programming voltage.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的单元晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 单元晶体管具有源极，栅极和与之短接在一起的主体。 响应于位线和字线上的编程电压，编程操作导致在单元晶体管的源极和漏极之间发生穿透。 单元晶体管的沟道长度基本上小于存取晶体管的沟道长度。 在一个实施例中，存取晶体管是NFET，而单元晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，单元晶体管也是NFET。 各种实施例导致所需编程电压的降低。