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公开(公告)号：US07829407B2
公开(公告)日：2010-11-09
申请号：US11561488
申请日：2006-11-20
IPC分类号： H01L21/336 , H01L21/84 , H01L29/78
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
摘要翻译： 一种包括半导体材料的半导体器件，该半导体材料具有形成在该弯曲处的弯曲部和沟槽特征，以及至少部分地设置在沟槽特征中的栅极结构。 一种制造半导体结构的方法，包括在层上形成具有沟槽特征的半导体材料，在沟槽特征中至少部分地形成栅极结构，以及弯曲半导体材料，使得在反转沟道中的半导体材料中产生应力 栅结构的区域。
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公开(公告)号：US07795098B1
公开(公告)日：2010-09-14
申请号：US11873886
申请日：2007-10-17
IPC分类号： H01L21/336
CPC分类号： H01L29/78621 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/66772
摘要： An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substantially orthogonal to an edge of the first gate structure to form a first impurity region and performing a second ion implant at a direction different than that of the first ion implant and substantially orthogonal to an edge of the second gate structure to form a second impurity region under the edge of the second gate structure.
摘要翻译： 用于制造旋转场效应晶体管的装置和方法。 该方法包括提供包括彼此不平行的第一栅极结构和第二栅极结构的衬底。 该方法还包括执行基本上与第一栅极结构的边缘正交的第一离子注入以形成第一杂质区域，并且在不同于第一离子注入的方向上执行第二离子注入并且基本上垂直于第 第二栅极结构，以在第二栅极结构的边缘下方形成第二杂质区域。
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公开(公告)号：US07659579B2
公开(公告)日：2010-02-09
申请号：US11539288
申请日：2006-10-06
IPC分类号： H01L29/78
CPC分类号： H01L29/78612 , H01L29/66772 , H01L29/78621 , H01L29/78648
摘要： A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.
摘要翻译： FET具有浅电源/漏极区域，深沟道区域，栅极堆叠和被电介质包围的背栅极。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。 因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。 还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。 该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。
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54.发明申请FET HAVING HIGH-K, VT MODIFYING CHANNEL AND GATE EXTENSION DEVOID OF HIGH-K AND/OR VT MODIFYING MATERIAL, AND DESIGN STRUCTURE 审中-公开具有高K，VT改性通道的FET和高K和/或VT修饰材料的栅极延伸和设计结构公开(公告)号：US20090236632A1
公开(公告)日：2009-09-24
申请号：US12051049
申请日：2008-03-19
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/4908 , H01L29/42384 , H01L29/78687
摘要： A field effect transistor (FET) including a high dielectric constant (high-k), threshold voltage (Vt) modifying channel and a gate extension devoid of the high-k and/or Vt modifying material, and a related design structure, are disclosed. In one embodiment, a FET may include a gate having a channel region thereunder including a gate insulator portion of a high dielectric constant (high-k) material and a threshold voltage (Vt) modifying portion (e.g., of SiGe); and a gate extension having a region thereunder devoid of at least one of the high-k material or the Vt modifying portion.
摘要翻译： 公开了包括高介电常数（high-k），阈值电压（Vt）修正通道和没有高k和/或Vt修饰材料的栅极延伸的场效应晶体管（FET）以及相关的设计结构 。 在一个实施例中，FET可以包括其下具有沟道区的栅极，其中包括高介电常数（高k）材料的栅极绝缘体部分和阈值电压（Vt）修改部分（例如SiGe）; 以及具有其上没有高k材料或Vt修改部分中的至少一个的区域的栅极延伸部。
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公开(公告)号：US20090197382A1
公开(公告)日：2009-08-06
申请号：US12023347
申请日：2008-01-31
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26546 , H01L21/26586 , H01L21/845 , H01L29/66803 , H01L29/785
摘要： Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that they are approximately perpendicular to the centerline. Then, masked implant sequences are performed, during which halo and/or source/drain dopants are implanted into the sidewalls of the semiconductor fins on one side of the chevron layout and then into the sidewalls of the semiconductor fins on the opposite side of the chevron layout. The implant direction used during these implant sequences is substantially orthogonal to the gates in order to avoid mask shadowing, which can obstruct dopant implantation when separation between the semiconductor fins in the chevron layout is scaled (i.e., when device density is increased).
摘要翻译： 本文公开了在高密度，人字纹图案化的CMOS器件中形成具有高迁移率晶面的p型和n型MUGFET的改进方法的实施方案。 具体地，半导体散热片形成为沿着晶片的中心线定向的人字形布局。 门形成在半导体翅片附近，使得它们大致垂直于中心线。 然后，进行掩蔽的植入序列，在此期间将卤素和/或源极/漏极掺杂剂注入到人字形布局的一侧上的半导体鳍片的侧壁中，然后进入人字纹相反侧的半导体鳍片的侧壁 布局。 在这些植入序列期间使用的植入方向基本上与栅极正交，以避免掩模阴影，当阴影布局中的半导体鳍片之间的间隔被缩放时（即，当器件密度增加时），这可能阻碍掺杂剂注入。
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56.发明申请FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 有权具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法公开(公告)号：US20090101978A1
公开(公告)日：2009-04-23
申请号：US11873521
申请日：2007-10-17
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译： 这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料 （例如，金属硅化物）。 以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。 以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。
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公开(公告)号：US07259590B1
公开(公告)日：2007-08-21
申请号：US11276169
申请日：2006-02-16
IPC分类号： H03K19/0185
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.
摘要翻译： 提供了一种用于为集成电路芯片的多电压岛/核心架构提供驱动器的系统和方法。 互补金属氧化物半导体（CMOS）逆变器由高阈值电压p沟道场效应晶体管（hi-Vt PFET）和规则阈值电压n沟道场效应晶体管（NFET）构成，其使用最大正值 电源（Vdd）在芯片上。 基于最大Vdd，驱动CMOS反相器的电压岛/芯的Vdd和hi-Vt PFET的亚阈值泄漏电流要求来确定hi-Vt PFET的阈值电压。
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公开(公告)号：US07087966B1
公开(公告)日：2006-08-08
申请号：US10908583
申请日：2005-05-18
IPC分类号： H01L31/0392
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.
摘要翻译： 一种半导体结构及其形成方法。 该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。 该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等 ）。 前门的宽度大于后门的宽度。 前门和S / D区之间的电容小于后门和S / D区之间的电容。 前门和S / D区之间的距离大于后门和S / D区之间的距离。
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公开(公告)号：US08946027B2
公开(公告)日：2015-02-03
申请号：US13367725
申请日：2012-02-07
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.
摘要翻译： 鳍状场效应晶体管（FinFET）结构和制造FinFET的方法，其包括形成在沟道区的每个端部上的沟道区和源/漏（S / D）区的硅鳍，其中整个底表面 沟道区域接触下绝缘体的顶表面，S / D区的底表面接触下硅锗（SiGe）层的顶表面的第一部分。 FinFET结构还包括接触顶部表面的外部S / D区域和下部SiGe层的顶表面的每个S / D区域和第二部分的两个侧表面。 FinFET结构还包括形成在通道区域的顶表面和两个侧表面上的适形电介质的替代栅极或栅极堆叠。
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60.发明授权Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (VT) lowering and method of forming the structure 有权部分耗尽（PD）绝缘体上半导体（SOI）场效应晶体管（FET）结构，具有用于阈值电压（VT）降低的栅 - 体隧道电流区域和形成结构的方法公开(公告)号：US08698245B2
公开(公告)日：2014-04-15
申请号：US12967329
申请日：2010-12-14
申请人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
IPC分类号： H01L27/12
CPC分类号： H01L29/78 , H01L21/26506 , H01L29/32 , H01L29/66477 , H01L29/78612
摘要： Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.
摘要翻译： 公开了具有栅对体隧道电流区域（GTBTCR）的场效应晶体管的实施例和方法。 在一个实施例中，具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分，以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。 在另一个实施例中，半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括：与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。 具有第二导电类型的栅极穿过中心部分。
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