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    Dynamic fair queuing to support best effort traffic in an ATM network
    52.
    发明授权
    Dynamic fair queuing to support best effort traffic in an ATM network 失效
    动态公平排队，以支持ATM网络中的最佳流量

    公开(公告)号：US5629928A

    公开(公告)日：1997-05-13

    申请号：US570840

    申请日：1995-12-12

    申请人： Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

    发明人： Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

    IPC分类号： H04Q3/00 ,  H04L12/56

    CPC分类号： H04L12/5602 ,  H04L47/10 ,  H04L49/3081 ,  H04L2012/5619 ,  H04L2012/5635 ,  H04L2012/5679

    摘要： A flow control apparatus implemented in a virtual path ATM communication system comprising a plurality of nodes interconnected by physical links which comprise virtual paths including a plurality of virtual channels. A connection between two nodes is defined as the combination of a physical link, a virtual path, and a virtual channel. Connections are shared between a reserved bandwidth service and a best effort service. ATM data cells conveyed on said best effort service are routed from node to node by analyzing their virtual connection identifier. Queues, allocated as needed from a pool of free queues, are used to store all incoming ATM data cells having the same virtual channel identifier.

    摘要翻译： 一种在虚拟路径ATM通信系统中实现的流控制装置，包括由包括多个虚拟信道的虚拟路径的物理链路互连的多个节点。 两个节点之间的连接被定义为物理链路，虚拟路径和虚拟信道的组合。 连接在保留的带宽服务和尽力而为的服务之间共享。 通过分析其虚拟连接标识符，在所述尽力服务上传送的ATM数据单元从节点路由到节点。 根据需要从空闲队列池分配的队列用于存储具有相同虚拟信道标识符的所有传入ATM数据单元。

    Apparatus for generating and checking the error correction codes of messages in a message switching system
    53.
    发明授权
    Apparatus for generating and checking the error correction codes of messages in a message switching system 失效
    用于在消息交换系统中生成和检查消息的纠错码的装置

    公开(公告)号：US5467359A

    公开(公告)日：1995-11-14

    申请号：US24061

    申请日：1993-03-01

    申请人： Pierre J. Huon ,  Philippe Jachimcsyk ,  Gerard Barucchi ,  Jean Calvignac ,  Fabrice Verplanken

    发明人： Pierre J. Huon ,  Philippe Jachimcsyk ,  Gerard Barucchi ,  Jean Calvignac ,  Fabrice Verplanken

    IPC分类号： G06F11/10 ,  G06F13/00 ,  H03M13/00 ,  H04L1/00

    CPC分类号： H04L1/0057 ,  H04L1/0041 ,  H04L2001/0094

    摘要： An error correction apparatus includes an error control circuit which computes for each burst of a message (for a destination unit) an error correction code as a function of an initial error correction code at the first burst of the message or of the error correction code of the previous burst and of the data bytes of the burst. The burst error correction code is sent on a medium which is separate from the data transport medium as a companion of the burst. Also, the error control circuit receives the burst error correction code from an origin unit and generates the burst error correction code to be compared with the received burst error correction code. If a mismatch is detected, the burst found in error is flagged.

    摘要翻译： 纠错装置包括：错误控制电路，用于根据消息的第一个突发或者纠错码的初始纠错码，对消息的每个突发（对于目的地单元）计算纠错码，作为初始纠错码的函数 先前的突发和突发的数据字节。 突发纠错码在与数据传输介质分离的介质上发送，作为突发的伴侣。 此外，误差控制电路从原点单元接收脉冲串纠错码，并产生与接收脉冲串纠错码进行比较的脉冲串纠错码。 如果检测到不匹配，则会发现错误中发现的突发状况。

    STM-1 TO STM-64 SDH/SONET FRAMER WITH DATA MULTIPLEXING FROM A SERIES OF CONFIGURABLE I/O PORTS
    55.
    发明申请
    STM-1 TO STM-64 SDH/SONET FRAMER WITH DATA MULTIPLEXING FROM A SERIES OF CONFIGURABLE I/O PORTS 有权
    STM-1到STM-64 SDH / SONET框架，具有从一系列可配置I / O端口进行数据多路复用

    公开(公告)号：US20060285551A1

    公开(公告)日：2006-12-21

    申请号：US11467848

    申请日：2006-08-28

    申请人： Kenneth Barker ,  Rolf Clauberg ,  Jean Calvignac ,  Andreas Herkersdorf ,  Fabrice Verplanken ,  David Webb

    发明人： Kenneth Barker ,  Rolf Clauberg ,  Jean Calvignac ,  Andreas Herkersdorf ,  Fabrice Verplanken ,  David Webb

    IPC分类号： H04J3/22

    CPC分类号： H04J3/1611 ,  H04J3/0685 ,  H04J3/22 ,  H04J2203/0089

    摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port snning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.

    摘要翻译： 本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种 单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或 根据SDH / SONET标准的STM-N定义更高。 更进一步地，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中而不是SDH，对应于156Mb / s的STM-1的三分之一的51.5Mb / s的数据速率。 根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口捕捉单元 其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

    Method and system for a timing based logic entry
    59.
    发明授权
    Method and system for a timing based logic entry 失效
    基于定时的逻辑输入的方法和系统

    公开(公告)号：US06789234B2

    公开(公告)日：2004-09-07

    申请号：US10328355

    申请日：2002-12-23

    申请人： Jean-Paul Aldebert ,  Jean Calvignac ,  Fabrice Verplanken

    发明人： Jean-Paul Aldebert ,  Jean Calvignac ,  Fabrice Verplanken

    IPC分类号： G06F1750

    CPC分类号： G06F17/5031

    摘要： A method and system for creating on a computer a timing based representation of an integrated circuit using a graphical editor operating on the computer. The method includes first in creating timing diagrams identifying the elements of the circuit and their time based interconnections. The method further comprises a translation of the timing based diagram editor files into HDL statement. The preferred embodiment is described, it comprises the use of an ASCII editor and a translation program to VHDL statements. A system is also described implementing the steps of the method in a computer. In order to avoid having different tools to translate timing based diagram editor files into HDL statements, a first step translating graphical editor output file into a PostScript file is performed by executing the “print to file” command of the printing driver of the computer. The PostScript file is then translated into a bitmap file using a RIP. The translation is then performed from the bitmap file into the HDL statements. This translation is “universal” as it can be used for any type of initial graphical file containing the timing diagram.

    摘要翻译： 一种用于在计算机上创建使用在计算机上操作的图形编辑器的基于时序的集成电路表示的方法和系统。 该方法首先在创建识别电路的元件及其基于时间的互连的时序图。 该方法还包括将基于时序的编辑器文件转换为HDL语句。 描述了优选实施例，它包括使用ASCII编辑器和对VHDL语句的翻译程序。 还描述了在计算机中实现该方法的步骤的系统。 为了避免使用不同的工具将基于时序的图编辑器文件转换为HDL语句，将图形编辑器输出文件转换为PostScript文件的第一步是通过执行计算机打印驱动程序的“打印到文件”命令执行的。 然后使用RIP将PostScript文件转换为位图文件。 然后，转换从位图文件执行到HDL语句。 这个翻译是“通用的”，因为它可以用于包含时序图的任何类型的初始图形文件。

    Data switch
    60.
    发明授权
    Data switch 失效
    数据开关

    公开(公告)号：US06195335B1

    公开(公告)日：2001-02-27

    申请号：US09110917

    申请日：1998-07-06

    申请人： Jean Calvignac ,  Daniel Orsatti ,  Gilles Toubol ,  Fabrice Verplanken ,  Claude Basso

    发明人： Jean Calvignac ,  Daniel Orsatti ,  Gilles Toubol ,  Fabrice Verplanken ,  Claude Basso

    IPC分类号： H04L1256

    CPC分类号： H04L12/5601 ,  H04L49/1576 ,  H04L2012/5679 ,  H04L2012/5681

    摘要： A packet data switch is described comprising a crossbar switch fabric including a set of crosspoint buffers for storing at least one data packet, one for each input/output pair. An input queue is provided for each input-output pair and means are provided for storing incoming data packets in one of the queues corresponding to an input-output routing for the data packet. An input scheduler repeatedly selects one queue from the plurality of queues at each input and a data packet is transferred from the queue selected by the input scheduler from the input queue means to the crosspoint buffer corresponding to the input-output routing for the data packet. A back pressure mechanism is arranged to inhibit selection by the first selector of queues corresponding to input/output pairs for which the respective crosspoint buffer is full. Finally, an output scheduler repeatedly selects for each output one of the crosspoint buffers corresponding to the output and the switch is responsive to the output scheduler to complete the transmission through the switch fabric of the data packet stored in the crosspoint buffer selected by the output scheduler.

    摘要翻译： 描述包数据交换机，其包括交叉开关结构，其包括用于存储至少一个数据分组的一组交叉点缓冲器，每个数据分组一个用于每个输入/输出对。 为每个输入 - 输出对提供输入队列，并且提供装置用于在对应于数据分组的输入 - 输出路由的一个队列中存储输入数据分组。 输入调度器在每个输入处重复从多个队列中选择一个队列，并且将数据分组从输入调度器选择的队列从输入队列装置传送到对应于数据分组的输入 - 输出路由的交叉点缓冲区。 背压机构被布置为禁止第一选择器对应于相应交叉点缓冲器已满的输入/输出对的队列的选择。 最后，输出调度器针对每个输出重复选择对应于输出的交叉点缓冲器之一，并且交换机响应于输出调度器来完成通过存储在由输出调度器选择的交叉点缓冲器中的数据分组的交换结构的传输 。