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    Buried decoupling capacitors, devices and systems including same, and methods of fabrication
    51.
    发明申请
    Buried decoupling capacitors, devices and systems including same, and methods of fabrication 有权
    掩埋去耦电容器，包括其的器件和系统以及制造方法

    公开(公告)号：US20080048231A1

    公开(公告)日：2008-02-28

    申请号：US11510945

    申请日：2006-08-28

    申请人： Badih El-Kareh

    发明人： Badih El-Kareh

    IPC分类号： H01L29/94

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5223 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

    摘要翻译： 提供了一种埋地去耦电容器装置和方法。 根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。 该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。 该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。 根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。

    Method of forming high performance lateral PNP transistor with buried base contact
    55.
    发明授权
    Method of forming high performance lateral PNP transistor with buried base contact 失效
    形成具有埋地基接触的高性能横向PNP晶体管的方法

    公开(公告)号：US5198376A

    公开(公告)日：1993-03-30

    申请号：US909938

    申请日：1992-07-07

    申请人： Sridhar Divakaruni ,  Badih El-Kareh ,  Eric D. Johnson

    发明人： Sridhar Divakaruni ,  Badih El-Kareh ,  Eric D. Johnson

    IPC分类号： H01L21/331

    CPC分类号： H01L29/6625 ,  Y10S148/096

    摘要： A high performance PNP lateral bipolar transistor is described, incorporating at least two trenches extending from the upper P.sup.- surface of a semiconductor substrate almost to a buried N.sup.+ layer. The floor of one trench is heavily N-doped to establish a connection between the buried N.sup.+ layer and an N.sup.- diffusion in the walls of the trench. When the trenches are backfilled with P.sup.+ polysilicon a lateral PNP is formed having a buried base contact.

    摘要翻译： 描述了一种高性能PNP横向双极晶体管，其包括从半导体衬底的上P-表面几乎延伸到掩埋的N +层的至少两个沟槽。 一个沟槽的底部被大量N掺杂以在掩埋的N +层和沟槽的壁中的N-扩散之间建立连接。 当沟槽用P +多晶硅回填时，形成具有掩埋基底接触的横向PNP。

    Method of making a contact to a trench isolated device
    56.
    发明授权
    Method of making a contact to a trench isolated device 失效
    与沟槽隔离装置接触的方法

    公开(公告)号：US4725562A

    公开(公告)日：1988-02-16

    申请号：US844655

    申请日：1986-03-27

    申请人： Badih El-Kareh ,  Richard R. Garnache ,  Ashwin K. Ghatalia

    发明人： Badih El-Kareh ,  Richard R. Garnache ,  Ashwin K. Ghatalia

    IPC分类号： H01L21/76 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/082 ,  H01L21/302

    CPC分类号： H01L21/76237 ,  H01L21/743

    摘要： A method or process is provided for making a semiconductor structure which includes the steps of forming in a semiconductor body a P/N junction and an opening in an insulating layer disposed on the surface of the semiconductor body. A trench is then formed in the semiconductor layer having a sidewall located along a given plane through the opening and through the P/N junction. An insulating material is disposed within the trench and over the insulating layer and a block or segment of material is located over the trench so as to extend a given distance from the trench over the upper surface of the body. The insulating material and the block are then etched so as to remove the block and the insulating material located along the sides of the block. A layer of low viscosity material is formed over the semiconductor body so as to cover the remaining portion of the insulating material, the layer of low viscosity material and the insulating material having similar etch rates. The layer of low viscosity material and the insulating material are then simultaneously etched directionally until all of the layer of low viscosity material is removed. Metallic contacts may now be formed on the surface of the semiconductor body without the concern that the metallic material will seep or enter into the trench causing a short at the P/N junction.

    摘要翻译： 提供了一种用于制造半导体结构的方法或工艺，该半导体结构包括以下步骤：在半导体本体中形成P / N结和设置在半导体本体表面上的绝缘层中的开口。 然后在半导体层中形成沟槽，该沟槽具有沿着给定平面穿过开口并通过P / N结的侧壁。 绝缘材料设置在沟槽内并在绝缘层之上，并且材料块或段被定位在沟槽上方，以便在主体的上表面上从沟槽延伸给定的距离。 然后蚀刻绝缘材料和块，以便去除沿着块的侧面定位的块和绝缘材料。 在半导体主体上形成一层低粘度材料，以覆盖绝缘材料的剩余部分，低粘度材料层和具有相似蚀刻速率的绝缘材料。 然后同时对低粘度材料层和绝缘材料层进行定向蚀刻，直到所有的低粘度材料层被去除。 现在可以在半导体本体的表面上形成金属接触，而不用担心金属材料将渗入或进入沟槽，导致P / N结处的短路。

    Memory devices with isolation structures
    58.
    发明授权
    Memory devices with isolation structures 有权
    具有隔离结构的存储器件

    公开(公告)号：US08654592B2

    公开(公告)日：2014-02-18

    申请号：US11811702

    申请日：2007-06-12

    申请人： Badih El-Kareh ,  Leonard Forbes

    发明人： Badih El-Kareh ,  Leonard Forbes

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： H01L27/11524 ,  G11C16/0408 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/66825 ,  H01L29/7881

    摘要： Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures.

    摘要翻译： 公开了存储器件及其编程和形成方法。 在一个实施例中，存储器件具有包含在介质隔离结构内的存储器单元，以将它们与至少与其它位线通信的那些存储器单元隔离，以便于正向偏置写入操作。 电介质隔离结构包含具有第一导电类型的上阱和具有第二导电类型的掩埋阱。 通过将接头从掩埋阱向上偏置到上阱，电子可以被注入到包含在介质隔离结构内的存储器单元的电荷存储节点中。

    Buried decoupling capacitors, devices and systems including same, and methods of fabrication
    59.
    发明授权
    Buried decoupling capacitors, devices and systems including same, and methods of fabrication 有权
    掩埋去耦电容器，包括其的器件和系统以及制造方法

    公开(公告)号：US08114753B2

    公开(公告)日：2012-02-14

    申请号：US12975761

    申请日：2010-12-22

    申请人： Badih El-Kareh

    发明人： Badih El-Kareh

    IPC分类号： H01L21/20

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5223 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

    摘要翻译： 提供了一种埋地去耦电容器装置和方法。 根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。 该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。 该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。 根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。