公开(公告)号：US06502196B1

公开(公告)日：2002-12-31

申请号：US09436590

申请日：1999-11-09

申请人： Nai-Shung Chang ,  Jang-Lih Hsieh

发明人： Nai-Shung Chang ,  Jang-Lih Hsieh

IPC分类号： G06F126

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172

摘要： A voltage converter for supporting a suspension-to-RAM (STR) mode of power management. The voltage converter has a flip-flop, a resume & initialization logic circuit for producing a resume signal, a STR logic circuit for producing a STR signal, a first voltage-conversion unit and a second voltage-conversion unit. An output terminal of the resume & initialization logic circuit is connected to a first input terminal of the flip-flop. An output terminal of the STR logic circuit is connected to a second input terminal of the flip-flop. An output terminal of the flip-flop is connected to the first voltage-conversion unit, and a complementary output terminal of the flip-flop is connected to the second voltage-conversion unit. A suspension voltage or a power voltage is applied to the voltage pin of a system memory depending on the mode of power management.

摘要翻译： 一种用于支持电源管理的悬挂到RAM（STR）模式的电压转换器。 电压转换器具有触发器，用于产生恢复信号的恢复和初始化逻辑电路，用于产生STR信号的STR逻辑电路，第一电压转换单元和第二电压转换单元。 恢复和初始化逻辑电路的输出端连接到触发器的第一输入端。 STR逻辑电路的输出端连接到触发器的第二输入端。 触发器的输出端子连接到第一电压转换单元，并且触发器的互补输出端子连接到第二电压转换单元。 取决于电源管理的模式，将悬架电压或电源电压施加到系统存储器的电压引脚。

公开(公告)号：US06470416B2

公开(公告)日：2002-10-22

申请号：US09336012

申请日：1999-06-18

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1200

CPC分类号： G06F13/161

摘要： A memory access control method and system is provided for use on a computer system having a CPU and a memory unit for controlling the memory access operation by the CPU to the memory unit. The memory unit is of the type having an auto-precharge feature. By this method and system, a CPU interface is coupled to the CPU, which is capable of promptly issuing an internal read-request signal in response to each read request from the CPU and is further capable of generating a cross-page signal concurrently with the internal read-request signal in the event that the data requested by the read request are located in a closed page in the memory unit. Furthermore, a memory control unit is coupled between the CPU interface and the memory unit, which is capable of issuing a normal read-enable signal to the memory unit in the event that the next internal read-request signal is received without having an accompanying cross-page signal before the read operation for the current read request is performed, and is further capable of issuing a read-with-auto-precharge enable signal to the memory unit in the event that the next internal read-request signal is received together with an accompanying cross-page signal before the read operation for the current read request is performed, the read-with-auto-precharge enable signal causing the memory unit to perform an auto-precharging operation after the read operation for the current read request is completed.

摘要翻译： 提供了一种在具有CPU和存储单元的计算机系统上使用的存储器访问控制方法和系统，用于控制CPU对存储器单元的存储器访问操作。 存储单元是具有自动预充电功能的类型。 通过该方法和系统，CPU接口耦合到CPU，CPU能够响应于来自CPU的每个读取请求而迅速地发出内部读取请求信号，并且还能够与所述CPU同时产生跨页面信号 在读取请求所请求的数据位于存储器单元中的闭合页面的情况下，内部读取请求信号。 此外，存储器控制单元耦合在CPU接口和存储器单元之间，其能够在接收到下一个内部读取请求信号而没有伴随的交叉的情况下向存储器单元发出正常的读取使能信号 在执行当前读取请求的读取操作之前的页面信号，并且还能够在下一个内部读取请求信号被接收的情况下向存储器单元发出读取自动预充电使能信号， 执行用于当前读取请求的读取操作之前的伴随的跨页信号，在完成当前读取请求的读取操作之后，使得自动预充电使能信号使存储器单元执行自动预充电操作 。

公开(公告)号：US06411123B1

公开(公告)日：2002-06-25

申请号：US09404624

申请日：1999-09-23

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F738

CPC分类号： G06F13/4072

摘要： A multi-option setting device is provided for use in association with a connecting pin of a chipset for the purpose of allowing user-selection from more than two setting options to set the chipset to perform one of more than two I/O functions through the associated connecting pin. The multi-option setting device includes voltage setting means for generating a user-specified input voltage; a voltage comparison circuit for use to determine which prespecified voltage range the user-specified input voltage lies; a latch circuit for latching the output of the voltage comparison circuit; and a control unit for setting the connecting pin to the user-selected I/O function corresponding to the user-specified input voltage. The user-specified input voltage is obtained from an externally-connected voltage divider and is compared by the voltage comparison circuit to determine which voltage range the user-specified input voltage lies to thereby generate an output logic signal whose value corresponds to the desired option. This allows the associated connecting pin to be optionally set to be used for a user-specified I/O function. Preferably, the connecting pin is a loudspeaker connecting pin. This multi-option setting device allows the user to select from more than two options, while nevertheless allowing the overall system to operate normally without being affected by the setting.

摘要翻译： 提供多选项设置装置，用于与芯片组的连接引脚相关联，以便允许来自多于两个设置选项的用户选择来设置芯片组以通过以下方式执行多于两个的I / O功能中的一个： 相关连接引脚。 多选项设定装置包括用于产生用户指定的输入电压的电压设定装置; 电压比较电路，用于确定用户指定的输入电压所在的哪个预定电压范围; 用于锁存电压比较电路的输出的锁存电路; 以及用于将连接引脚设置为与用户指定的输入电压相对应的用户选择的I / O功能的控制单元。 用户指定的输入电压从外部连接的分压器获得，并通过电压比较电路进行比较，以确定用户指定的输入电压所在的电压范围，从而生成其值对应于期望选项的输出逻辑信号。 这允许相关联的连接引脚可选地设置为用于用户指定的I / O功能。 优选地，连接销是扬声器连接销。 该多选项设置设备允许用户从两个以上的选项中进行选择，同时允许整个系统正常运行而不受设置的影响。

公开(公告)号：US06384346B1

公开(公告)日：2002-05-07

申请号：US09688037

申请日：2000-10-12

申请人： Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho ,  Chia-Hsing Yuo ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho ,  Chia-Hsing Yuo ,  Shu-Hui Chen

IPC分类号： H01R909

CPC分类号： H05K7/1459 ,  H05K1/0216 ,  H05K2201/044 ,  H05K2201/09236

摘要： A trace layout of a printed circuit board (PCB) is provided with a north bridge, at least a peripheral component interconnect (PCI) slot, and an accelerate graphics port (AGP) slot. The PCB includes at least a first trace layer and a second trace layer under the first trace layer. The AGP slot is mounted between the north bridge and the PCI slot. The PCB further includes a number of first traces, and a number of second traces. The first traces are used for connecting the north bridge to the PCI slot while the second traces are used to connect the north bridge to the AGP slot. Some of the first traces are on the second trace layer under the AGP slot, while the other of the first traces are on the first trace layer or the second trace layer and trace aside the AGP slot. Most of the second traces are on the first trace layer and the other of the second traces are on the second trace layer.

摘要翻译： 印刷电路板（PCB）的迹线布局提供有北桥，至少外围组件互连（PCI）插槽和加速图形端口（AGP）插槽。 PCB包括至少第一迹线层和第一迹线层下的第二迹线层。 AGP插槽安装在北桥和PCI插槽之间。 PCB还包括多个第一迹线和多个第二迹线。 第一条迹线用于将北桥连接到PCI插槽，而第二条路径用于将北桥连接到AGP插槽。 一些第一个迹线位于AGP插槽下的第二个跟踪层上，而第一个迹线中的另一个迹线位于第一个跟踪层或第二个跟踪层上，并跟踪AGP插槽。 大多数第二迹线位于第一迹线层上，而第二迹线中的另一条迹线位于第二迹线层上。

公开(公告)号：US06377510B2

公开(公告)日：2002-04-23

申请号：US09756586

申请日：2001-01-09

申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： G11C700

CPC分类号： G06F13/1694

摘要： A memory control system for controlling write-enable signals. The memory control system has a first memory slot having a write-enable pin thereon, a second memory slot having a first write-enable pin and a second write-enable pin thereon and a control chipset having a write-enable pin and a dual-purpose write-enable/memory-parity-data pin thereon. The write-enable pin of the control chipset is connected to the write-enable pin of the first memory slot and the first write-enable pin of the second memory slot. The write-enable/memory-parity-data pin of the control chipset is connected to the second write-enable pin of the second memory slot. In this invention, since the design of the write-enable system is more flexible, length of trace line on a computer board can be greatly reduced. In addition, the system permits the incorporation of one cycle (1T) timing into design of memory access commands.

摘要翻译： 一种用于控制写使能信号的存储器控​​制系统。 存储器控制系统具有在其上具有写使能引脚的第一存储器插槽，其上具有第一写使能引脚和第二写使能引脚的第二存储器插槽以及具有写使能引脚和双引脚引脚的控制芯片组， 目的写入/存储器奇偶校验数据引脚。 控制芯片组的写使能引脚连接到第一存储器插槽的写使能引脚和第二存储器插槽的第一写使能引脚。 控制芯片组的写使能/存储器奇偶校验数据引脚连接到第二存储器插槽的第二写使能引脚。 在本发明中，由于写使能系统的设计更灵活，所以可以大大减少计算机板上的迹线长度。 此外，该系统允许将一个周期（1T）定时并入到存储器访问命令的设计中。

公开(公告)号：US6084425A

公开(公告)日：2000-07-04

申请号：US96057

申请日：1998-06-11

申请人： Yuantsang Liaw ,  Ching-Fu Chuang ,  Nai-Shung Chang

发明人： Yuantsang Liaw ,  Ching-Fu Chuang ,  Nai-Shung Chang

IPC分类号： H03H7/40 ,  G01R19/00

CPC分类号： H03H7/40

摘要： An impedance adjusting apparatus of a controlling chip on a computer mainboard. When a computer is turned on, BIOS automatically detects the actual usage of the memory sockets, and then sends corresponding control signals to adjust the impedance of the impedance adjusting apparatus for a better impedance matching between the controlling chip and the memory sockets. The signal reflection is dramatically reduced and the operation bandwidth is widened.

摘要翻译： 一种在计算机主板上的控制芯片的阻抗调节装置。 当计算机打开时，BIOS会自动检测内存插槽的实际使用情况，然后发送相应的控制信号，调整阻抗调整装置的阻抗，以便控制芯片和存储器插槽之间更好的阻抗匹配。 信号反射明显减少，工作带宽扩大。

公开(公告)号：US20100191988A1

公开(公告)日：2010-07-29

申请号：US12752201

申请日：2010-04-01

申请人： Nai-Shung Chang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Chia-Hsing Yu

IPC分类号： G06F1/00

CPC分类号： G06F1/324 ,  G06F1/3225 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.

摘要翻译： 提供了一种降低处于工作状态的计算机系统的功耗的方法。 计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。 该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电 通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。 当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

公开(公告)号：US20090121352A1

公开(公告)日：2009-05-14

申请号：US12354152

申请日：2009-01-15

申请人： Chih-Hsiung Lin ,  Nai-Shung Chang

发明人： Chih-Hsiung Lin ,  Nai-Shung Chang

IPC分类号： H01L23/498

CPC分类号： H01L23/367 ,  H01L23/3677 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/15321

摘要： A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.

摘要翻译： 一种用于多封装模块的封装衬底。 封装衬底包括具有管芯区域和从管芯区域向外延伸到衬底的边缘的至少一个热通道区域的衬底。 凸起之间的间隔比热通道区域的宽度窄，在芯片和热通道区域之外的基板上配置有凸块排列。 还公开了一种具有封装基板的电子器件。

公开(公告)号：US20070288769A1

公开(公告)日：2007-12-13

申请号：US11423718

申请日：2006-06-13

申请人： Nai-Shung Chang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Chia-Hsing Yu

IPC分类号： G06F1/00

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/124 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for dynamically increasing the data processing capability of a computer system is provided. The computer system comprises a processor, a memory and a chipset. The data processing capability of the computer system is classified into a predetermined number of performance enhancing modes. At least one performance enhancing mode transition condition is checked to determine whether to automatically raise the performance enhancing mode of the computer system. The processor is suspended from using the processor bus during the transition of the performance enhancing mode of the computer system. The performance enhancing mode of the computer system is raised by increasing a first working frequency of the processor, a second working frequency of the processor bus and a third working frequency of the memory. The data processing rate of the computer system is further increased when the performance enhancing mode of the computer system is further raised.

摘要翻译： 提供了一种用于动态提高计算机系统的数据处理能力的方法。 计算机系统包括处理器，存储器和芯片组。 计算机系统的数据处理能力被分为预定数量的性能增强模式。 检查至少一个性能增强模式转换条件以确定是否自动提高计算机系统的性能增强模式。 处理器在计算机系统的性能提升模式转换期间被暂停使用处理器总线。 通过增加处理器的第一工作频率，处理器总线的第二工作频率和存储器的第三工作频率来提高计算机系统的性能增强模式。 当计算机系统的性能提升模式进一步提高时，计算机系统的数据处理速度进一步提高。

公开(公告)号：US20070045804A1

公开(公告)日：2007-03-01

申请号：US11292631

申请日：2005-12-02

申请人： Chih-Hsiung Lin ,  Nai-Shung Chang

发明人： Chih-Hsiung Lin ,  Nai-Shung Chang

IPC分类号： H01L23/02

CPC分类号： H05K1/0209 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/15321 ,  H05K1/0206 ,  H05K1/0207 ,  H05K2201/066 ,  H05K2201/09309 ,  H05K2201/09781 ,  H05K2201/10734

摘要： A printed circuit board (PCB) with an improved thermal dissipating structure for a package substrate of a multi-package module (MPM). A first upper metal layer is on a substrate and corresponds to the package substrate. A second upper metal layer is on the substrate outside the package substrate. An inner metal layer is in the substrate. Pluralities of first and second heat conductive vias are in the substrate to thermally connect the inner metal layer to the first and second upper metal layers, respectively. An electronic device with an improved thermal dissipating structure is also disclosed.

摘要翻译： 一种用于多封装模块（MPM）的封装衬底的具有改进的散热结构的印刷电路板（PCB）。 第一上金属层位于衬底上并对应于封装衬底。 第二上金属层位于封装衬底外的衬底上。 内部金属层位于基板中。 多个第一和第二导热通孔位于衬底中，以将内部金属层分别热连接到第一和第二上部金属层。 还公开了一种具有改善的散热结构的电子设备。