公开(公告)号：US05998290A

公开(公告)日：1999-12-07

申请号：US097353

申请日：1998-06-15

申请人： Zhiqiang Wu ,  Pai-Hung Pan

发明人： Zhiqiang Wu ,  Pai-Hung Pan

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/3205

CPC分类号： H01L21/28061 ,  H01L29/4941 ,  H01L29/4983 ,  H01L21/32137 ,  Y10S257/90 ,  Y10S257/915

摘要： A process of manufacturing a gate stack whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.

摘要翻译： 制造栅极堆叠的工艺，由此保持栅极侧壁和衬底表面的完整性。 氮化物间隔物构造在仅蚀刻到多晶硅层顶部的栅极的侧壁上。 这允许在随后的再氧化期间暴露更多的多晶硅侧壁，同时最小化在再氧化期间产生的鸟嘴的影响。 在构造氮化物间隔物之后，以两个步骤进行随后的蚀刻，以便使底层活性区域中的衬底表面的降解最小化。

公开(公告)号：US5985766A

公开(公告)日：1999-11-16

申请号：US807192

申请日：1997-02-27

申请人： Zhiqiang Wu ,  Alan R. Reinberg ,  Manny Ma

发明人： Zhiqiang Wu ,  Alan R. Reinberg ,  Manny Ma

IPC分类号： H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76838 ,  H01L21/76877

摘要： The invention provides methods for forming contact openings to a substrate location with which electrical connection is desired. According to one aspect, a multi-level layer comprising masking material or photoresist is formed atop an electrically conductive substrate surface and defines a mask opening through which a contact opening is to be formed to an elevationally lower substrate location. A single layer of photoresist is patterned to form an elevationally thicker first layer immediately laterally adjacent the mask opening than a second layer which is formed laterally outward of the first layer. The electrically conductive substrate surface is etched through the mask opening to form the contact opening. The photoresist second layer is removed and the conductive substrate surface is etched to form a portion of an outer conductive component. Thereafter, conductive material is formed in the contact opening to electrically connect elevationally separated layers. According to another aspect, a masking material layer comprises a bi-level profile having two different layer elevational thicknesses, the greater of which being disposed immediately laterally adjacent a contact opening pattern. A contact opening is etched through the substrate outer surface and conductive material is formed therein to electrically connect the substrate location with an outer conductive layer. In a preferred implementation, the masking material layer or photoresist is formed through photolithography using only a single mask. In another implementation, more than one mask is used to define the multi-level or bi-level profile masking material layer. The multi-level masking layer can have more than two levels.

公开(公告)号：US5946595A

公开(公告)日：1999-08-31

申请号：US818637

申请日：1997-03-14

申请人： Trung T. Doan ,  Zhiqiang Wu ,  Li Li

发明人： Trung T. Doan ,  Zhiqiang Wu ,  Li Li

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76895 ,  H01L21/28518

摘要： Disclosed is a method for forming a local interconnect with a self-aligned titanium silicide process on a semiconductor substrate. The initial step of the method is to form a thin titanium layer over the electronic devices to be provided with electrical communication. A polysilicon layer is then formed over the thin titanium layer, and in a further step, an implant mask is formed over portions of the polysilicon layer so as to pattern an area where the local interconnect is desired to be formed. Ions are then implanted into the polysilicon layer exposed by the implant mask, and the implant mask is then removed. In a further step, an etch process that etches either implanted or unimplanted polysilicon and is selective to the other is conducted. The remaining implanted polysilicon and titanium layers are then annealed to form titanium silicide, and the titanium that is not converted to titanium silicide is removed.

摘要翻译： 公开了一种在半导体衬底上形成具有自对准钛硅化物工艺的局部互连的方法。 该方法的初始步骤是在电子设备上形成薄钛层以提供电通信。 然后在薄钛层上形成多晶硅层，并且在另一步骤中，在多晶硅层的部分上形成注入掩模，以便图案化需要形成局部互连的区域。 然后将离子注入由植入掩模暴露的多晶硅层中，然后移除植入物掩模。 在另一步骤中，进行蚀刻植入或未投影多晶硅并且对另一个选择性的蚀刻工艺。 然后将剩余的注入的多晶硅和钛层退火以形成硅化钛，并且除去未转化为硅化钛的钛。

公开(公告)号：US5946564A

公开(公告)日：1999-08-31

申请号：US912108

申请日：1997-08-04

申请人： Zhiqiang Wu ,  Luan C. Tran ,  Robert Kerr ,  Shubneesh Batra ,  Rongsheng Yang

发明人： Zhiqiang Wu ,  Luan C. Tran ,  Robert Kerr ,  Shubneesh Batra ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807

摘要： Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain regions within one well region of a substrate; and well contact diffusion regions within another well region of the substrate. The common masking step preferably defines at least one mask opening over the substrate within which the well contact diffusion region is to be formed, and the mask opening is suitably dimensioned to reduce the amount of halo ion implantation dopant which ultimately reaches the substrate therebelow. According to one aspect, a plurality of mask openings are provided. According to another aspect, a suitably-dimensioned single mask opening is provided. In yet another aspect, a unique well region construction is provided with one or more complementary mask openings which is (are) configured to, in connection with the provision of the halo ion implantation dopant, block the amount of implantation dopant which ultimately reaches the substrate adjacent the well contact diffusion regions. Accordingly, at least some of the well contact diffusion region(s) remain in substantial contact with the well region after the doping of the substrate with the halo ion implantation dopant.

摘要翻译： 描述了形成集成电路的集成电路和方法。 在一个实现中，利用公共掩模步骤来相对于衬底的一个阱区域内的源极/漏极区域提供源极/漏极扩散区域和晕圈离子注入或掺杂区域; 以及在衬底的另一个阱区域内的良好接触扩散区域。 常见的掩蔽步骤优选地限定在其上将要形成阱接触扩散区的衬底上的至少一个掩模开口，并且掩模开口被适当地设定尺寸以减少最终到达衬底的卤素离子注入掺杂剂的量。 根据一个方面，提供了多个掩模开口。 根据另一方面，提供了适当尺寸的单个掩模开口。 在另一方面，独特的井区结构设置有一个或多个互补掩模开口，其被配置为与提供卤素离子注入掺杂剂相结合，阻止最终到达衬底的注入掺杂剂的量 邻近阱接触扩散区。 因此，在用卤素离子注入掺杂剂掺杂衬底之后，至少一些阱接触扩散区域保持与阱区基本接触。

公开(公告)号：USD1030460S1

公开(公告)日：2024-06-11

申请号：US29860979

申请日：2022-11-24

申请人： Zhiqiang Wu

设计人： Zhiqiang Wu

摘要： FIG. 1 is a front perspective view of a caster, showing my new design;
FIG. 2 is a rear perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top view thereof;
FIG. 8 is a bottom view thereof;
FIG. 9 is a front perspective view thereof, shown in an environment of use; and,
FIG. 10 is a front perspective view thereof, shown in another environment of use.
The broken lines in the drawings illustrate the portions of the caster, which form no part of the claimed design.

公开(公告)号：US09062430B2

公开(公告)日：2015-06-23

申请号：US13318282

申请日：2011-06-27

申请人： Jiwen Peng ,  Zhiqiang Wu ,  Weichan Tan ,  Wei Zhao

发明人： Jiwen Peng ,  Zhiqiang Wu ,  Weichan Tan ,  Wei Zhao

IPC分类号： E01C19/00 ,  E02D3/046 ,  E01C19/34 ,  E01C19/30 ,  E02D3/054

CPC分类号： E02D3/046 ,  E01C19/30 ,  E01C19/34 ,  E02D3/054 ,  F16C35/06 ,  F16C2300/14 ,  F16C2350/00

摘要： A buffer unit for the slewing platform of the tamping machine, comprising a slewing plafform, a slewing bearing and a chassis, the upper end of the said slewing bearing connects to the slewing plafform and the lower end of said slewing bearing connects to the chassis, the slewing platform can revolve around the chassis 360 degrees, further comprising a annular supporting slab, a hydraulic cylinder and a connecting rod, the annular supporting slab is fixed on the chassis by bolt. The hydraulic cylinder is fitted on the rear end of the central plane of the slewing platform, the piston rod head of the hydraulic cylinder connects to said connecting rod. The connecting rod can touch and support the annular base slab at any point of the direction of 360 degrees rotation when the hydraulic cylinder extends.

摘要翻译： 一种用于捣固机的回转平台的缓冲单元，包括回转平台，回转支承和底盘，所述回转支承的上端连接到回转平板，而所述回转支承的下端连接到底盘， 回转平台可围绕底盘360度旋转，还包括环形支撑板，液压缸和连杆，环形支撑板通过螺栓固定在底盘上。 液压缸安装在回转平台的中心平面的后端，液压缸的活塞杆头连接到所述连杆。 当液压缸延伸时，连杆可以在360度旋转方向的任何点处接触并支撑环形基板。

公开(公告)号：US09043809B2

公开(公告)日：2015-05-26

申请号：US13463406

申请日：2012-05-03

申请人： Zhiqiang Wu ,  Christian Weiss ,  Joerg Singler

发明人： Zhiqiang Wu ,  Christian Weiss ,  Joerg Singler

IPC分类号： G06F17/30 ,  G06F9/54

CPC分类号： G06F3/0484 ,  G06F17/30569 ,  G06F17/30876 ,  H04L67/10 ,  H04L67/32

摘要： The disclosure generally describes computer-implemented methods, software, and systems for allowing provisioning of open data protocol (OData) services on top of a generic interaction layer (GenIL). One computer-implemented method includes receiving an OData-compliant request for data, determining a GenIL data provider to receive the OData-compliant request for data, determining the memory location of the data, requesting the data from the determined memory location, receiving the requested data from the determined memory location, converting, using at least one computer, the received data into an OData-compliant format, rendering an OData-compliant response, and transmitting the OData-compliant response.

摘要翻译： 本公开通常描述了用于允许在通用交互层（GenIL）之上提供开放数据协议（OData）服务的计算机实现的方法，软件和系统。 一种计算机实现的方法包括接收关于数据的OData兼容请求，确定GenIL数据提供者接收对数据的OData兼容请求，确定数据的存储器位置，从所确定的存储器位置请求数据，接收所请求的 来自所确定的存储器位置的数据，使用至少一个计算机将所接收的数据转换为符合OData的格式，呈现与OData兼容的响应，以及发送与OData兼容的响应。

公开(公告)号：US08501570B2

公开(公告)日：2013-08-06

申请号：US12981610

申请日：2010-12-30

申请人： Ziwei Fang ,  Jeff J. Xu ,  Ming-Jie Huang ,  Yimin Huang ,  Zhiqiang Wu ,  Min Cao

发明人： Ziwei Fang ,  Jeff J. Xu ,  Ming-Jie Huang ,  Yimin Huang ,  Zhiqiang Wu ,  Min Cao

IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7848 ,  H01L21/02057 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.

摘要翻译： 用于制造集成电路器件的集成电路器件和方法通过在第一掺杂区域中形成第二掺杂区域并且去除第一和第二掺杂区域，从而提供对用于形成集成电路器件的源极和漏极特征的沟槽形状的改进的控制 第二掺杂区域通过第一和第二湿蚀刻工艺。

公开(公告)号：US08338259B2

公开(公告)日：2012-12-25

申请号：US12750160

申请日：2010-03-30

申请人： Zhiqiang Wu ,  Jeffrey Junhao Xu ,  Chih-Hao Chang ,  Wen-Hsing Hsieh

发明人： Zhiqiang Wu ,  Jeffrey Junhao Xu ,  Chih-Hao Chang ,  Wen-Hsing Hsieh

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.

摘要翻译： 提供了具有局部应力源的半导体器件，例如PMOS或NMOS器件。 凹槽形成在栅电极的相对侧上。 沿着凹部的底部形成应力诱导区域，在应力诱导区域上形成应力层。 通过具有比应力层更大的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生拉伸应变，并且可以适用于NMOS器件。 通过具有比应力层更小的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生压应变，并且可以适用于PMOS器件。 实施例可以应用于各种类型的基板和半导体器件，例如平面晶体管和finFET。

公开(公告)号：US08114727B2

公开(公告)日：2012-02-14

申请号：US12549862

申请日：2009-08-28

申请人： Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

发明人： Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

IPC分类号： H01L21/00

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).

摘要翻译： 一种用于使用应力存储技术（SMT）层（126）形成NMOS晶体管（104）和嵌入式SiGe（eSiGe）PMOS晶体管（102）的集成工艺流程。 SMT层（126）沉积在NMOS晶体管（104）和PMOS晶体管（102）两者之上。 在PMOS晶体管（102）上方的SMT层（126）的部分被各向异性蚀刻以形成间隔物（128），而不通过NMOS晶体管（104）蚀刻SMT层（126）的部分。 间隔物（128）用于对准SiGe凹陷蚀刻和生长以形成SiGe源极/漏极区域（132）。 在蚀刻SMT层（126）之后执行源极/漏极退火，使得SMT层（126）在不降低PMOS晶体管（102）的情况下向NMOS晶体管（104）提供期望的应力。