公开(公告)号：US08350673B2

公开(公告)日：2013-01-08

申请号：US12364158

申请日：2009-02-02

申请人： Sheshidher Nyalamadugu ,  Jun Liu ,  Francisco Martinez de Velasco Cortina

发明人： Sheshidher Nyalamadugu ,  Jun Liu ,  Francisco Martinez de Velasco Cortina

IPC分类号： H04Q5/22

CPC分类号： G06K7/10277 ,  G06K19/073 ,  G06K19/07345 ,  G06K19/0739 ,  H01Q1/2208 ,  H01Q9/0414 ,  H01Q21/28

摘要： A card comprises an antenna configured to generate and receive radio frequency signals, a chip coupled with the antenna, the chip configured to store sensitive information and communicate the information to an authorized reader via the antenna, and a switching mechanism configured to tune and detune the antenna relative to the chip to enable and disable respectively, the chips ability to communicate the sensitive information via the antenna.

公开(公告)号：US08344890B2

公开(公告)日：2013-01-01

申请号：US11962047

申请日：2007-12-20

申请人： Jeffrey Zhu ,  Chih-chuan Yen ,  Jun Liu ,  Joe Mullis

发明人： Jeffrey Zhu ,  Chih-chuan Yen ,  Jun Liu ,  Joe Mullis

IPC分类号： G08B13/14 ,  G08B23/00

CPC分类号： G06K19/07758 ,  G06K19/07749 ,  G06K19/07773 ,  G08B13/2434

摘要： In the embodiments described herein, a RFID enabled license plate is constructed by using the license plate, or a retro-reflective layer formed thereon as part of the resonator configured to transmit signals generated by and RFID chip integrated with the license plate. Such an RFID enabled license plate can include a metal license plate with a slot formed in the metal license plate, and a RFID tag module positioned in the slot. The RFID tag module can include a chip and a loop, and the loop can be coupled with the metal license plate, e.g., via inductive or conductive coupling. In this manner, the metal license plate can be configured to act as a resonator providing increased performance.

公开(公告)号：US20120325492A1

公开(公告)日：2012-12-27

申请号：US13602928

申请日：2012-09-04

申请人： Michael Fefer ,  Jun Liu ,  Heinz Mueller ,  Nadja Herzog ,  Diana Maeker

发明人： Michael Fefer ,  Jun Liu ,  Heinz Mueller ,  Nadja Herzog ,  Diana Maeker

IPC分类号： C09K8/06 ,  E21B43/00 ,  E21B7/00 ,  E21B41/00 ,  C09K8/18 ,  E21B17/00

CPC分类号： C09K8/36 ,  C09K8/18 ,  C09K8/34 ,  E21B7/00 ,  E21B10/00 ,  E21B21/00 ,  E21B21/01 ,  E21B43/00

摘要： A drilling composition is provided. The composition includes: I) an organic phase comprising components: i. from about 20 wt. % to about 99.999 wt. %, based on the total weight of components i. and ii., of at least one linear or branched, cyclic or non-cyclic, saturated hydrocarbon; ii. from about 0.001 wt. % to about 25 wt. %, based on the total weight of components i. and ii., of at least one ester; II) from 0 to about 50 wt. %, based on the total weight of the composition, of water or aqueous phase; III) from 0 to about 60 wt. %, based on the total weight of the composition, of at least one additive, wherein the sum of the weight components I) to III) is 100 wt. %.

摘要翻译： 提供钻井组合物。 组合物包括：I）包含组分的有机相：i。 约20wt。 ％至约99.999重量％ ％，基于组件i的总重量。 和ii。至少一种直链或支链，环状或非环状饱和烃; ii。 约0.001重量％ ％至约25wt。 ％，基于组件i的总重量。 和ii。至少一种酯; II）为0至约50wt。 ％，基于组合物的总重量，水或水相; III）为0至约60wt。 ％，基于组合物的总重量，至少一种添加剂，其中重量组分I）至III）之和为100重量％。 ％。

公开(公告)号：US08335100B2

公开(公告)日：2012-12-18

申请号：US11812004

申请日：2007-06-14

申请人： Jun Liu ,  David Porter

发明人： Jun Liu ,  David Porter

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass through a coupled resistive memory cell when a voltage drop applied to the access device is greater than a critical voltage. The array may be biased to reduce standby currents and improve delay times between programming and read operations.

摘要翻译： 公开了方法，系统，结构和阵列，例如包括接入装置（例如背对背齐纳二极管）的电阻式存储器阵列，其仅当电压降施加到电阻时才允许电流通过耦合的电阻存储器单元 接入设备大于临界电压。 该阵列可能被偏置以减少待机电流并改善编程和读取操作之间的延迟时间。

公开(公告)号：US20120313615A1

公开(公告)日：2012-12-13

申请号：US13590819

申请日：2012-08-21

申请人： Jun Liu ,  Haibo Zhang

发明人： Jun Liu ,  Haibo Zhang

IPC分类号： G05F3/02

CPC分类号： H02M3/156

摘要： An integrated circuit includes a saw-tooth generator including a saw tooth node configured to have a saw-tooth voltage generated thereon; and a first switch having a first end connected to the saw tooth node. The integrated circuit further includes a second switch coupled between an output node and an electrical ground, wherein the first switch and the second switch are configured to operate synchronously. A first current source is connected to the saw tooth node. A second current source is connected to the output node.

摘要翻译： 集成电路包括锯齿发生器，其包括被配置为具有在其上产生的锯齿电压的锯齿节点; 以及第一开关，其具有连接到锯齿节点的第一端。 集成电路还包括耦合在输出节点和电接地之间的第二开关，其中第一开关和第二开关被配置为同步地操作。 第一电流源连接到锯齿节点。 第二个电流源连接到输出节点。

公开(公告)号：US20120248557A1

公开(公告)日：2012-10-04

申请号：US13079652

申请日：2011-04-04

申请人： Jun Liu ,  Gurtej Sandhu

发明人： Jun Liu ,  Gurtej Sandhu

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

摘要： Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

摘要翻译： 提供了减少存储单元损坏的技术。 通常使用破坏存储单元结构的某些区域的干蚀刻和/或平坦化处理来形成存储单元结构。 在一个或多个实施例中，细胞结构的某些区域可能对损伤敏感。 例如，磁存储单元结构中的自由磁区可能易于退磁。 这样的区域在形成存储单元结构期间可以基本上被阻挡材料限制，使得这些区域的边缘被保护免受损坏的过程。 此外，在一些实施例中，存储单元结构形成并限制在电介质材料的凹部内。

公开(公告)号：US08263367B2

公开(公告)日：2012-09-11

申请号：US12020071

申请日：2008-01-25

申请人： Yijun Ruan ,  Chialin Wei ,  Melissa Jane Fullwood ,  Jun Liu

发明人： Yijun Ruan ,  Chialin Wei ,  Melissa Jane Fullwood ,  Jun Liu

IPC分类号： C07H22/00 ,  C12P19/34

CPC分类号： C12N15/1065 ,  C12Q1/6804 ,  C12Q1/6806 ,  C12Q2525/191 ,  C12Q2525/186 ,  C12Q2523/101

摘要： The present invention provides at least one isolated linear composite nucleic acid molecule comprising at least one first tag from at least one first nucleic acid molecule and at least one second tag from at least one second nucleic acid molecule, wherein the first and second nucleic acids interact in a nucleic acid mixture; and wherein the first and second tags are from different nucleic acid molecules. The invention also provides a method of producing at least one isolated linear composite nucleic acid and to a method of detecting and/or identifying nucleic acid interactions.

摘要翻译： 本发明提供至少一种分离的线性复合核酸分子，其包含来自至少一个第一核酸分子的至少一个第一标签和至少一个第二核酸分子的至少一个第二标签，其中所述第一和第二核酸相互作用 在核酸混合物中; 并且其中所述第一和第二标签来自不同的核酸分子。 本发明还提供了生产至少一种分离的线性复合核酸的方法以及检测和/或鉴定核酸相互作用的方法。

公开(公告)号：US08258828B2

公开(公告)日：2012-09-04

申请号：US12938150

申请日：2010-11-02

申请人： Jun Liu ,  Haibo Zhang

发明人： Jun Liu ,  Haibo Zhang

IPC分类号： H03K4/90

CPC分类号： H02M3/156

摘要： An integrated circuit includes a saw-tooth generator including a saw tooth node configured to have a saw-tooth voltage generated thereon; and a first switch having a first end connected to the saw tooth node. The integrated circuit further includes a second switch coupled between an output node and an electrical ground, wherein the first switch and the second switch are configured to operate synchronously. A first current source is connected to the saw tooth node. A second current source is connected to the output node.

摘要翻译： 集成电路包括锯齿发生器，其包括被配置为具有在其上产生的锯齿电压的锯齿节点; 以及第一开关，其具有连接到锯齿节点的第一端。 集成电路还包括耦合在输出节点和电接地之间的第二开关，其中第一开关和第二开关被配置为同步地操作。 第一电流源连接到锯齿节点。 第二个电流源连接到输出节点。

公开(公告)号：US08243506B2

公开(公告)日：2012-08-14

申请号：US12869338

申请日：2010-08-26

申请人： Jun Liu

发明人： Jun Liu

IPC分类号： G11C11/00 ,  H01L29/02

CPC分类号： H01L45/126 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/144 ,  H01L45/16

摘要： Methods, devices, and systems associated with phase change memory structures are described herein. One method of forming a phase change memory structure includes forming an insulator material on a first conductive element and on a dielectric material of a phase change memory cell, forming a heater self-aligned with the first conductive element, forming a phase change material on the heater and at least a portion of the insulator material formed on the dielectric material, and forming a second conductive element of the phase change memory cell on the phase change material.

摘要翻译： 本文描述了与相变存储器结构相关联的方法，装置和系统。 形成相变存储器结构的一种方法包括在第一导电元件上和在相变存储器单元的电介质材料上形成绝缘体材料，形成与第一导电元件自对准的加热器，在第一导电元件上形成相变材料 加热器和形成在电介质材料上的绝缘体材料的至少一部分，以及在相变材料上形成相变存储器单元的第二导电元件。

公开(公告)号：US08233316B2

公开(公告)日：2012-07-31

申请号：US12561896

申请日：2009-09-17

申请人： Jun Liu

发明人： Jun Liu

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/003 ,  G11C17/16 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： An improved memory array architecture and cell design in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The other of the channel terminals are effectively tied together via reference lines. The word lines (i.e., gates) of the two access transistors are also tied together. The result in a preferred embodiment is a cell having two access transistors wired and accessed in parallel. With such a configuration, the widths of the access transistors can be made one-half the width of more-traditional one-access-transistor designs, saving layout space in that (first) dimension. Moreover, because the word lines of adjacent cells will be deselected, the improved design does not require cell-to-cell isolation (e.g., trench isolation) in the other (second) dimension. The result, when applied to a phase change memory, comprises about a 37% reduction in layout area from previous cell designs.

摘要翻译： 改进的存储器阵列架构和单元设计，其中单元采用两个存取晶体管。 在一个实施例中，每个单元中的两个存取晶体管在其一个通道端子处耦合到存储元件，存储元件又连接到位线。 另一个通道终端通过参考线实际连接在一起。 两个存取晶体管的字线（即，门）也被连接在一起。 在优选实施例中的结果是具有并联连接和访问的两个存取晶体管的单元。 通过这样的配置，可以使存取晶体管的宽度成为传统的一次存取晶体管设计的宽度的一半，从而节省了（第一）尺寸的布局空间。 此外，由于相邻单元的字线将被取消选择，所以改进的设计不需要另一（第二）尺寸的单元间隔离（例如沟槽隔离）。 结果，当应用于相变存储器时，包括比以前的单元设计大约减少37％的布局面积。