公开(公告)号：US20140115206A1

公开(公告)日：2014-04-24

申请号：US13658976

申请日：2012-10-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Oren Tzvi Sela ,  Noam Bloch

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/423 ,  G06F2213/0026

Abstract: Methods and devices for running network protocols over Peripheral Component Interconnect Express are disclosed. The methods and devices may receive an electronic signal comprising data. The methods and devices may also determine the data corresponds to a protocol selected from a set comprising a PCIe protocol and a network protocol. In addition, the methods and devices may also configure a CPU based on the determined protocol. The methods and devices may also receive a second electronic signal comprising second data at a pin or land of the CPU, wherein the pin or land is connected to a PCIe lane and wherein the second data is formatted in accordance with determined protocol. In addition, the methods and devices may process the second data in accordance with the determined protocol.

Abstract translation: 披露了通过Peripheral Component Interconnect Express运行网络协议的方法和设备。 方法和装置可以接收包括数据的电子信号。 方法和设备还可以确定对应于从包括PCIe协议和网络协议的集合中选择的协议的数据。 此外，方法和设备还可以基于所确定的协议来配置CPU。 所述方法和设备还可以接收包括在CPU的引脚或引脚上的第二数据的第二电子信号，其中所述引脚或引脚连接到PCIe通道，并且其中根据所确定的协议对第二数据进行格式化。 此外，方法和装置可以根据确定的协议处理第二数据。

公开(公告)号：US12259832B2

公开(公告)日：2025-03-25

申请号：US18174668

申请日：2023-02-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

IPC: G06F13/28 ,  G06F3/06

Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

公开(公告)号：US12107767B2

公开(公告)日：2024-10-01

申请号：US17715167

申请日：2022-04-07

Applicant: Mellanox Technologies Ltd.

Inventor： Yuval Shpigelman ,  Idan Borshteen ,  Noam Bloch

IPC: H04L47/25 ,  H04L43/106 ,  H04L47/263 ,  H04L47/283

CPC classification number: H04L47/25 ,  H04L43/106 ,  H04L47/263 ,  H04L47/283

Abstract: A device and method may alter the transmission rate of data sent across a computer network based on a time to receive an acknowledgement in response to a packet sent over the network. An embodiment may transmit packets across the computer network according to a rate R, where R is determined based at least on a number of bytes to be sent during a window (cwnd) divided by a duration of time (RTT); and modify RTT based on a current round trip time of a packet sent over the network (e.g. based on a time to receive an acknowledgement in response to a packet sent over the network).

公开(公告)号：US11870590B2

公开(公告)日：2024-01-09

申请号：US17107990

申请日：2020-12-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Roee Moyal ,  Ariel Shahar ,  Noam Bloch ,  Ran Koren

IPC: H04L1/18 ,  H04L1/1829 ,  G06F15/173

CPC classification number: H04L1/1829 ,  G06F15/17331

Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.

公开(公告)号：US20220377014A1

公开(公告)日：2022-11-24

申请号：US17874352

申请日：2022-07-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch

IPC: H04L45/745 ,  H04L69/22 ,  G06F13/42

Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.

公开(公告)号：US20220283964A1

公开(公告)日：2022-09-08

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G06F12/1045 ,  G06F15/173 ,  G06F9/46 ,  G06F9/455

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US11102129B2

公开(公告)日：2021-08-24

申请号：US16559640

申请日：2019-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Noam Bloch ,  Roee Moyal ,  Ariel Shahar ,  Yamin Friedman ,  Yuval Shpigelman

IPC: H04L12/28 ,  H04L12/801 ,  H04L12/927 ,  H04L12/863 ,  H04L29/08 ,  H04L12/841

Abstract: A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.

公开(公告)号：US20210243121A1

公开(公告)日：2021-08-05

申请号：US16780940

申请日：2020-02-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch

IPC: H04L12/741 ,  G06F13/42 ,  H04L29/06

Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.

公开(公告)号：US20190149486A1

公开(公告)日：2019-05-16

申请号：US16181376

申请日：2018-11-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dror Bohrer ,  Noam Bloch ,  Peter Paneah ,  Richard Graham

IPC: H04L12/879 ,  H04L12/883 ,  H04L12/861 ,  H04L12/935

Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.

公开(公告)号：US20190132085A1

公开(公告)日：2019-05-02

申请号：US15796803

申请日：2017-10-29

Applicant: Mellanox Technologies, Ltd.

Inventor： Alexander Shpiner ,  Adi Menachem ,  Eitan Zahavi ,  Noam Bloch ,  Ariel Shahar

IPC: H04L1/08 ,  H04L1/16 ,  H04L1/18

Abstract: A network element processes a data flow in accordance with a communications protocol in which respective incremental sequence numbers are assigned to segments of the data flow. The segments are sent from the network element to the other network element in order of the sequence numbers, and respective acknowledgements are received from the other network element. The acknowledgements may include the highest sequence number of the segments of the flow that were received in the other network element. After transmitting the last segment of the data flow an additional segment is sent to the other network element. When it is determined from an acknowledgement of the additional segment that the last segment of the data flow was not received by the other network element, the last segment is retransmitted.