公开(公告)号：US20200379908A1

公开(公告)日：2020-12-03

申请号：US16424421

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/0837 ,  G06F12/1027 ,  G06F12/1009 ,  G06F11/14 ,  G06F9/38

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

公开(公告)号：US20200326880A1

公开(公告)日：2020-10-15

申请号：US16382511

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G11C15/04 ,  G11C13/00

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.

公开(公告)号：US20190035453A1

公开(公告)日：2019-01-31

申请号：US16019483

申请日：2018-06-26

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel

IPC: G11C11/406 ,  G11C11/22

CPC classification number: G11C11/40615 ,  G11C11/1675 ,  G11C11/22 ,  G11C11/2275 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/408 ,  G11C13/0004 ,  G11C13/0016 ,  G11C13/0033

Abstract: Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages having an refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.

公开(公告)号：US20190007529A1

公开(公告)日：2019-01-03

申请号：US15989920

申请日：2018-05-25

Applicant: Micron Technology, Inc.

Inventor： Kenneth M. Curewitz ,  Sean Eilert ,  Ameen D. Akel ,  Hongyu Wang

IPC: H04L29/06 ,  G06F3/06 ,  G06F9/38

Abstract: A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device.

公开(公告)号：US20250165160A1

公开(公告)日：2025-05-22

申请号：US19033755

申请日：2025-01-22

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Justin Eno ,  Ameen D. Akel

IPC: G06F3/06 ,  H03M13/09 ,  H03M13/11

Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

公开(公告)号：US12299291B2

公开(公告)日：2025-05-13

申请号：US17369869

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Justin Eno ,  Ameen D. Akel

IPC: H03M13/11 ,  G06F3/06 ,  H03M13/09

Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

公开(公告)号：US20240411466A1

公开(公告)日：2024-12-12

申请号：US18808887

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US20240370208A1

公开(公告)日：2024-11-07

申请号：US18778842

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivam Swami ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel ,  Sean Stephen Eilert

IPC: G06F3/06 ,  G06F12/02 ,  H10B63/00

Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.

公开(公告)号：US20240338149A1

公开(公告)日：2024-10-10

申请号：US18607283

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： Chun-Yi Liu ,  Ameen D. Akel ,  Lance P. Johnson

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673

Abstract: Methods, systems, and devices for schedule memory are described. Specifically, techniques are described for a memory interface between a host system and memory (e.g., a tightly coupled memory). For example, a memory interface block (MIB) between the host system and the memory system may schedule access operations performed by the memory system, schedule and perform error control operations, schedule and perform media management operations, as well as schedule and perform other operations. The use of such a MIB may enable the improvement of the memory system by reducing latency and increasing efficiency of memory accesses, while reducing impacts on the architecture and design of the host system.

公开(公告)号：US12105589B2

公开(公告)日：2024-10-01

申请号：US17652231

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: G06F11/10

CPC classification number: G06F11/108

Abstract: Methods, systems, and devices for parity-based error management are described. A processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. The processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.