公开(公告)号：US20250037773A1

公开(公告)日：2025-01-30

申请号：US18781618

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Xiangyu Yang ,  Yingda Dong

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08

Abstract: Apparatuses, systems, and methods for applying a read voltage overdrive. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a pass voltage to a wordline in the array of memory cells, apply a read voltage to the wordline, and apply a read voltage overdrive greater than the read voltage and less than or equal to the pass voltage to the wordline.

公开(公告)号：US20240248637A1

公开(公告)日：2024-07-25

申请号：US18412010

申请日：2024-01-12

Applicant: Micron Technology, Inc.

Inventor： Go Shikata ,  Xiangyu Yang ,  Ching-Huang Lu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device can include a memory array coupled with control logic. The control logic initiates a read operation on one or more memory cells of a plurality of memory cells arranged in one or more tiers. The control logic can further cause a read voltage to be applied to a selected wordline coupled to the one or more memory cells during the read operation. The control logic can cause a first voltage to be applied to a first set of unselected wordlines coupled to memory cells in a first tier of the one or more tiers during the read operation. The control logic can cause a second voltage to be applied to a second set of unselected wordlines coupled to memory cells in a second tier of the one or more tiers during the read operation, wherein the second voltage is less than the first voltage.

公开(公告)号：US20240242754A1

公开(公告)日：2024-07-18

申请号：US18402875

申请日：2024-01-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ching-Huang Lu ,  Go Shikata ,  Gangotree Chakma

IPC: G11C11/408 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C11/4076 ,  G11C11/4096

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including identifying a set of parameters related to the memory device, selecting, based on the set of parameters, a magnitude of a bias voltage to be applied to a global wordline during a read state transition of a block of the memory device from a transient state to a stable state, and causing the bias voltage to be applied to the global wordline.

公开(公告)号：US11967387B2

公开(公告)日：2024-04-23

申请号：US17970459

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US20240120010A1

公开(公告)日：2024-04-11

申请号：US18545888

申请日：2023-12-19

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

公开(公告)号：US20240071515A1

公开(公告)日：2024-02-29

申请号：US18235183

申请日：2023-08-17

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Quang Diep ,  Avinash Rajagiri ,  Yingda Dong

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483

Abstract: Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line. During the subset of erase loops, a first adjusted erase bias voltage is caused to be applied to the first select gate and a second adjusted erase bias voltage is caused to be applied to the second select gate.

公开(公告)号：US11894069B2

公开(公告)日：2024-02-06

申请号：US17591361

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Yang ,  Hong-Yan Chen ,  Ching-Huang Lu

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/30

Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

公开(公告)号：US20230268003A1

公开(公告)日：2023-08-24

申请号：US18103978

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Vinh Quang Diep ,  Jeffrey Ming-Hung Tsai ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/3459 ,  G11C16/08 ,  G11C16/0483

Abstract: A memory device comprising a memory array and control logic operatively coupled with the memory array. The control logic is to: detect a program operation directed at a selected wordline of multiple wordlines of the memory array; determine, during an initial phase of the program operation, whether a program voltage being applied to the selected wordline satisfies a threshold program voltage; add, in response to the program voltage not satisfying the threshold program voltage, a base offset voltage to an initial pass voltage to generate a higher pass voltage, the initial pass voltage being a percentage of an initial program voltage; and cause the higher pass voltage to be applied to a remainder of the multiple wordlines other than the selected wordline.

公开(公告)号：US20220189555A1

公开(公告)日：2022-06-16

申请号：US17247576

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.