公开(公告)号：US20230352098A1

公开(公告)日：2023-11-02

申请号：US18132489

申请日：2023-04-10

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Dheeraj Srinivasan ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Violante Moschiano

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/30

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, obtaining cell state information for each respective group of adjacent cells, for each target cell of the set of target cells, determining a state information bin of a set of state information bins based on the cell state information for its respective group of adjacent cells, and assigning each target cell of the set of target cells to the respective state information bin. Each state information bin of the set of state information bins defines a respective boost voltage level offset to be applied to perform boost voltage modulation.

公开(公告)号：US20230060312A1

公开(公告)日：2023-03-02

申请号：US17893364

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10

Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.

公开(公告)号：US20230043418A1

公开(公告)日：2023-02-09

申请号：US17514267

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  Ali Mohammadzadeh ,  Dheeraj Srinivasan ,  Daniel J. Hubbard ,  Luca Bert

IPC: G06F3/06

Abstract: Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

公开(公告)号：US20230018681A1

公开(公告)日：2023-01-19

申请号：US17951754

申请日：2022-09-23

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US11456039B2

公开(公告)日：2022-09-27

申请号：US17102876

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C7/10

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US11264099B2

公开(公告)日：2022-03-01

申请号：US17090067

申请日：2020-11-05

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Jeffrey M. Tsai ,  Ali Mohammadzadeh ,  Terry M. Grunzke

IPC: G11C16/08 ,  G06F3/06 ,  G11C16/12 ,  G11C8/08 ,  G11C16/14 ,  G11C16/30

Abstract: An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

公开(公告)号：US20220020435A1

公开(公告)日：2022-01-20

申请号：US16947091

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Dheeraj Srinivasan ,  Andrea D'Alessandro

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04

Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and one or more bitline driver circuits coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The one or more bitline driver circuits can perform a first pre-charging operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.

公开(公告)号：US20220011959A1

公开(公告)日：2022-01-13

申请号：US16946869

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F3/06 ,  G06F13/16

Abstract: A processing device in a memory sub-system determines whether to check a status of one or more memory dies of the memory device and sends a multi-unit status command to the memory device, the multi-unit status command specifying a plurality of memory units associated with the one or more memory dies of the memory device. The processing device further receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

公开(公告)号：US20210232508A1

公开(公告)日：2021-07-29

申请号：US17227473

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Michael G. Miller ,  Xiaoxiao Zhang ,  Jung Sheng Hoei

IPC: G06F12/1009 ,  G11C11/56 ,  G06F11/07 ,  G06F3/06 ,  G06F12/02

Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.

公开(公告)号：US10949291B2

公开(公告)日：2021-03-16

申请号：US16776600

申请日：2020-01-30

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: H03M7/04 ,  H03M13/05 ,  H03M13/09 ,  G06F11/10 ,  G11C11/56 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  H03M13/37 ,  G11C29/02

Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.