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公开(公告)号：US20200233585A1
公开(公告)日：2020-07-23
申请号：US16839721
申请日：2020-04-03
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Marco Dallabora , Paolo Amato , Danilo Caraccio , Daniele Balluchi
Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.
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公开(公告)号：US10705963B2
公开(公告)日：2020-07-07
申请号：US15927530
申请日：2018-03-21
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora , Roberto Izzi , Paolo Amato , Daniele Balluchi , Luca Porzio
IPC: G06F3/06 , G06F12/0862 , G06F12/10
Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.
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公开(公告)号：US20200152267A1
公开(公告)日：2020-05-14
申请号：US16744643
申请日：2020-01-16
Applicant: Micron Technology, Inc.
Inventor： Marco Dallabora , Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri
Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.
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公开(公告)号：US10573383B2
公开(公告)日：2020-02-25
申请号：US16124222
申请日：2018-09-07
Applicant: Micron Technology, Inc.
Inventor： Marco Dallabora , Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri
Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.
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公开(公告)号：US10430085B2
公开(公告)日：2019-10-01
申请号：US15345783
申请日：2016-11-08
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora
IPC: G06F3/06 , G06F12/1009 , G06F11/10 , G11C16/34
Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.
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Patent Agency Ranking
公开(公告)号：US20190294547A1
公开(公告)日：2019-09-26
申请号：US15927530
申请日：2018-03-21
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora , Roberto Izzi , Paolo Amato , Daniele Balluchi , Luca Porzio
IPC: G06F12/0862 , G06F12/10
Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.
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公开(公告)号：US20190294356A1
公开(公告)日：2019-09-26
申请号：US15927339
申请日：2018-03-21
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora , Roberto Izzi , Paolo Amato , Daniele Balluchi , Luca Porzio
IPC: G06F3/06
Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.
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公开(公告)号：US20180129442A1
公开(公告)日：2018-05-10
申请号：US15862472
申请日：2018-01-04
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Graziano Mirichigni , Gianfranco Santopietro , Gianfranco Ferrante , Emanuele Confalonieri
IPC: G06F3/06
CPC classification number: G06F3/0643 , G06F3/061 , G06F3/0679
Abstract: A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. The contextual file system data includes file metadata, file attributes, or both that identify an association of the one or more blocks of data with a file. The file is made up of the one or more blocks of data. The controller identifies the association of the one or more blocks of data with the file and executes the one or more commands, such that the one or more blocks of data are stored in the memory device with a placement based upon the association
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公开(公告)号：US20180129423A1
公开(公告)日：2018-05-10
申请号：US15345783
申请日：2016-11-08
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora
IPC: G06F3/06 , G06F12/1009 , G06F11/10
CPC classification number: G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0634 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/0683 , G06F11/1048 , G06F11/1076 , G06F12/1009 , G06F2212/65 , G11C16/3495
Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.
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公开(公告)号：US09201705B2
公开(公告)日：2015-12-01
申请号：US14247783
申请日：2014-04-08
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Emanuele Confalonieri , Federico Tiziani
CPC classification number: G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
Abstract translation: 各种实施例包括装置和方法，包括如由主机指导的在存储器装置中重新配置分区的方法。 该方法包括通过第一接口控制器管理命令以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。 描述附加的装置和方法。
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