公开(公告)号：US20200287003A1

公开(公告)日：2020-09-10

申请号：US16294759

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L29/16 ,  H01L29/207 ,  H01L29/08 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US20200286906A1

公开(公告)日：2020-09-10

申请号：US16810009

申请日：2020-03-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10734399B2

公开(公告)日：2020-08-04

申请号：US15858509

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Jin Chen ,  Guangyu Huang ,  Mojtaba Asadirad

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/11526 ,  G11C16/26 ,  G11C16/24 ,  G11C16/14 ,  G11C16/10 ,  H01L23/528 ,  H01L29/36 ,  H01L29/04 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L23/532 ,  G11C16/08 ,  G11C16/04 ,  H01L29/08

Abstract: Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.

公开(公告)号：US10734388B1

公开(公告)日：2020-08-04

申请号：US16248534

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/167

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US20200227428A1

公开(公告)日：2020-07-16

申请号：US16248248

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L21/28 ,  H01L23/532

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US20200219899A1

公开(公告)日：2020-07-09

申请号：US16822696

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra V. Mouli ,  Srinivas Pulugurtha

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/22 ,  H01L21/28

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

公开(公告)号：US20200152644A1

公开(公告)日：2020-05-14

申请号：US16188432

申请日：2018-11-13

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC: H01L27/1159 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L29/10 ,  H01L27/11592 ,  G11C11/22

Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions. The body region has a different semiconductor composition than at least one of the first and second source/drain regions to enable replenishment of carrier within the body region. An insulative material is along the body region. A ferroelectric material is along the insulative material. A conductive gate material is along the ferroelectric material.

公开(公告)号：US20200083245A1

公开(公告)日：2020-03-12

申请号：US16123538

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Mojtaba Asadirad

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.

公开(公告)号：US20200051638A1

公开(公告)日：2020-02-13

申请号：US16518687

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US10163908B2

公开(公告)日：2018-12-25

申请号：US15005360

申请日：2016-01-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L23/528

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.