公开(公告)号：US12105961B2

公开(公告)日：2024-10-01

申请号：US17978890

申请日：2022-11-01

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Sead Zildzic ,  Violante Moschiano ,  James Fitzpatrick

IPC: G06F3/06 ,  G11C16/34 ,  G11C29/52

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/3459 ,  G11C29/52

Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

公开(公告)号：US12073891B2

公开(公告)日：2024-08-27

申请号：US17682089

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Violante Moschiano ,  Jeffrey S. McNeil ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C16/102 ,  G11C16/26 ,  G11C2207/2254

Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.

公开(公告)号：US12040025B2

公开(公告)日：2024-07-16

申请号：US17675392

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Patrick R. Khayat ,  Hyung Seok Kim ,  Steven Michael Kientz

IPC: G11C11/34 ,  G06F11/07 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/073 ,  G06F11/0787 ,  G11C16/14 ,  G11C16/0483

Abstract: A system includes a memory device including an block and a processing device, operatively coupled with the memory device, to perform operations including initiating a page scan with respect to a page of the block, determining whether to perform an erased page check, and in response to determining that the erased page check is not to be performed, performing a two-sided page scan with calibration feedback.

公开(公告)号：US20240079035A1

公开(公告)日：2024-03-07

申请号：US18509088

申请日：2023-11-14

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Steven Michael Kientz ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu

IPC: G11C7/04 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C7/04 ,  G06F3/064 ,  G11C16/08 ,  G11C16/26

Abstract: A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

公开(公告)号：US20240029801A1

公开(公告)日：2024-01-25

申请号：US18211802

申请日：2023-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dung Viet Nguyen ,  Patrick R. Khayat ,  Zhengang Chen ,  Shantilal Rayshi Doru ,  Hope Abigail Henry

IPC: G11C16/34 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/26

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first metric characterizing threshold voltage distributions of a subset of the plurality of memory cells; determining a first read voltage adjustment; receiving a second metric characterizing the threshold voltage distributions; determining a second read voltage adjustment; and applying the second read voltage adjustment for reading the subset of the plurality of memory cells.

公开(公告)号：US20240004567A1

公开(公告)日：2024-01-04

申请号：US18370342

申请日：2023-09-19

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Steven Michael Kientz ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0625 ,  G06F3/0679

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

公开(公告)号：US20230268009A1

公开(公告)日：2023-08-24

申请号：US17675392

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Patrick R. Khayat ,  Hyung Seok Kim ,  Steven Michael Kientz

IPC: G11C16/26 ,  G11C16/14 ,  G06F11/07

CPC classification number: G11C16/26 ,  G11C16/14 ,  G06F11/0787 ,  G06F11/073 ,  G11C16/0483

Abstract: A system includes a memory device including an block and a processing device, operatively coupled with the memory device, to perform operations including initiating a page scan with respect to a page of the block, determining whether to perform an erased page check, and in response to determining that the erased page check is not to be performed, performing a two-sided page scan with calibration feedback.

公开(公告)号：US11709734B2

公开(公告)日：2023-07-25

申请号：US17246509

申请日：2021-04-30

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: G06F11/10 ,  G06F11/00 ,  H03M13/00

CPC classification number: G06F11/1076

Abstract: Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.

公开(公告)号：US20230062445A1

公开(公告)日：2023-03-02

申请号：US17682089

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Violante Moschiano ,  Jeffrey S. McNeil ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.

公开(公告)号：US11431355B2

公开(公告)日：2022-08-30

申请号：US17157141

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak

IPC: H03M13/00 ,  H03M13/29 ,  H03M13/15

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.