公开(公告)号：US4079330A

公开(公告)日：1978-03-14

申请号：US746336

申请日：1976-12-01

申请人： Yukinobu Ishigaki ,  Kohei Sasamura ,  Yasuo Itoh ,  Teruo Muraoka

发明人： Yukinobu Ishigaki ,  Kohei Sasamura ,  Yasuo Itoh ,  Teruo Muraoka

IPC分类号： G11B3/00 ,  H03D3/00 ,  H03D3/02 ,  H03D3/06 ,  H03D3/24 ,  H03D3/26 ,  H04H20/89 ,  H04S3/00 ,  H03D3/22

CPC分类号： H04H20/88 ,  H03D3/005 ,  H03D3/02 ,  H03D3/06 ,  H03D3/24 ,  H03D3/26 ,  H04H20/89

摘要： The inventive system demodulates angle-modulated signals. A tracking band-pass filter responds to an input angle-modulated wave signal. The tracking filter has a pass band with a center frequency controlled by a control signal. A first amplitude limiter limits the amplitude of the input angle-modulated wave signal. A differentiation circuit establishes a 90.degree. phase difference between a signal passing through the tracking band-pass filter and a signal passing through the amplitude limiter. A phase comparator responds to an input with the two signals with a 90.degree. phase difference therebetween and produces an output error signal in accordance with this phase difference. This output error signal is supplied as the control signal to the tracking band-pass filter. This output error signal is also passed through a low pass filter to produce the demodulated signal.

摘要翻译： 本发明的系统解调角度调制信号。 跟踪带通滤波器响应输入角度调制波信号。 跟踪滤波器具有通过控制信号控制的中心频率的通带。 第一幅度限制器限制输入角度调制波信号的幅度。 差分电路在通过跟踪带通滤波器的信号和通过幅度限制器的信号之间建立90°的相位差。 相位比较器响应输入，其中两个信号之间的相位差为90°，并根据该相位差产生输出误差信号。 该输出误差信号作为控制信号提供给跟踪带通滤波器。 该输出误差信号也通过低通滤波器以产生解调信号。

公开(公告)号：US4030533A

公开(公告)日：1977-06-21

申请号：US686362

申请日：1976-05-14

申请人： Yasuo Itoh ,  Yoshitake Suzuki ,  Hirohiko Shibutami ,  Koichi Hirano ,  Muneo Tagami

发明人： Yasuo Itoh ,  Yoshitake Suzuki ,  Hirohiko Shibutami ,  Koichi Hirano ,  Muneo Tagami

IPC分类号： B22D11/12 ,  B22D11/16 ,  B22D11/10

CPC分类号： B22D11/16 ,  B22D11/12 ,  B22D11/122

摘要： A continuous casting system provides with a foreign matter receiving gutter between two adjacent rolls to receive foreign matters dropping during the drawing operation of castings, and a foreign matter removing nozzle to wash away the foreign matter dropped on the gutter. An electromagnetic agitator of the continuous casting system is provided with a proximity switch at least at its inlet side to sense a magnetic substance approaching the agitator thereby to control the operation of the agitator, thus eliminating troubles caused by the vibration of the magnetic substance.

摘要翻译： 连续铸造系统在两个相邻的辊之间提供接收沟槽的异物，以在铸件的拉制操作期间接收异物掉落，以及异物去除喷嘴，以清除掉在沟槽上的异物。 连续铸造系统的电磁搅拌器至少在其入口侧设置有接近开关，以感测接近搅拌器的磁性物质，从而控制搅拌器的操作，从而消除由磁性物质的振动引起的麻烦。

公开(公告)号：US3983500A

公开(公告)日：1976-09-28

申请号：US502531

申请日：1974-09-03

申请人： Nobuaki Takahashi ,  Kazunori Nishikawa ,  Yoshiki Iwasaki ,  Masaaki Satoh ,  Katsuhiro Ohba ,  Shinji Nakamura ,  Tatsuo Sawada ,  Nobuhide Ohsaki ,  Yasuo Itoh ,  Nobuaki Suda ,  Yasuhisa Okabe ,  Hideaki Ozaki

发明人： Nobuaki Takahashi ,  Kazunori Nishikawa ,  Yoshiki Iwasaki ,  Masaaki Satoh ,  Katsuhiro Ohba ,  Shinji Nakamura ,  Tatsuo Sawada ,  Nobuhide Ohsaki ,  Yasuo Itoh ,  Nobuaki Suda ,  Yasuhisa Okabe ,  Hideaki Ozaki

IPC分类号： G11B20/00 ,  G11B23/00 ,  H03D3/24 ,  H04S3/00 ,  G11B3/04 ,  G11B3/74 ,  H03D3/00

CPC分类号： H03D3/244 ,  G11B20/00992 ,  G11B23/0007 ,  H04S3/006

摘要： An angle modulated wave demodulation system demodulates an input angle modulated wave by means of a phase locked loop system which comprises a phase comparator, which is operated responsive to an input angle modulated wave. A voltage controlled oscillator is supplied with a part of the output of the phase comparator which controls its oscillation frequency. The oscillator supplies its oscillation frequency to the phase comparator. The phase locked loop system has a lock frequency range which decreases its width when the level of the input angle modulated wave is below a predetermined level. The portion of this lock range in which the width of the lock range decreases is positively utilized. The voltage controlled oscillator oscillates at a frequency equal to the center frequency of the carrier of the input angle modulated wave, when the phase locked loop becomes unlocked.

公开(公告)号：US3940698A

公开(公告)日：1976-02-24

申请号：US361218

申请日：1973-05-17

申请人： Yasuo Itoh

发明人： Yasuo Itoh

IPC分类号： H03D3/04 ,  H03D5/00 ,  H03G3/34 ,  H04B1/10 ,  H04S3/00

CPC分类号： H03D5/00 ,  H03D3/04 ,  H03G3/34 ,  H04S3/006

摘要： A muting circuit comprises, substantially, a gate circuit for passing or not passing input signals and a circuit for forming a control signal for controlling the gating operation of the gate circuit. The control signal forming circuit has a circuit for detecting the level of a carrier wave in the input signal. A first time constant circuit has a very small time constant .tau..sub.1. A second time constant circuit exhibits a delay time constant of .tau..sub.2 (where .tau..sub.2 >>.tau..sub.1) when a carrier wave component exists in the input and a delay time constant which becomes substantially zero when a carrier wave component does not exist. A third time constant circuit of a time constant .tau..sub.3 (where .tau..sub.3 >.tau..sub.2) is with a 180.degree. phase relationship relative to the second time constant circuit.

摘要翻译： 静音电路基本上包括用于通过或不通过输入信号的门电路和用于形成用于控制门电路的选通操作的控制信号的电路。 控制信号形成电路具有用于检测输入信号中载波电平的电路。 第一时间常数电路具有非常小的时间常数τ1。当输入中存在载波分量时，第二时间常数电路表现出τ2的延迟时间常数（其中τ2 >>τ1）和延迟时间常数 当不存在载波分量时，其变为基本为零。 时间常数τ3（其中tau 3> tau 2）的第三次恒定电路相对于第二时间常数电路具有180°的相位关系。

公开(公告)号：US06493267B2

公开(公告)日：2002-12-10

申请号：US09836264

申请日：2001-04-18

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C7/1006 ,  G11C7/1048 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

摘要翻译： 一种非易失性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路，经由开关元件连接到触发器电路的位线，用于对位线充电的晶体管， 连接到位线并具有MOS晶体管结构的非易失性存储单元，用于当其阈值被设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，所述存储器单元的阈值为 当触发器电路保持在第一状态并且在触发器电路保持在第二状态时阈值的偏移不被影响，并且在验证时，从第一阈值范围向第二阈值范围移动 模式下，当阈值保持在第二阈值范围内时，位线由充电晶体管保持在充电电位，并且数据设置电路用于连接第一和第二信号节点之一 当位线在验证模式下处于电荷电位时，触发电路的电位达到预定电位，从而将触发器电路设置在第二状态，而与验证模式之前的状态无关。

公开(公告)号：US06259612B1

公开(公告)日：2001-07-10

申请号：US09665071

申请日：2000-09-19

申请人： Yasuo Itoh

发明人： Yasuo Itoh

IPC分类号： G05F110

CPC分类号： H02M3/07

摘要： An internal voltage generator generates an internal voltage that is obtained by up-converting or down-converting an external power supply voltage. A resistor-voltage divider, having a plurality of resistors, outputs a first divided voltage that is obtained by dividing the internal voltage according to a resistance ratio of the resistors. A capacitor-voltage divider, having a plurality of capacitors connected in series between an output terminal of the internal voltage generator and a ground level, outputs a second divided voltage from the capacitors. A comparator compares a reference voltage and the first divided voltage for controlling the internal voltage generator according to a result of comparison. The comparator judges whether to halt operation of the internal voltage generator or not based on the result of comparison between the reference voltage and the first divided voltage while the internal voltage generator is operating. On the other hand, the comparator operates the internal voltage generator based on the result of comparison between the reference voltage and the second divided voltage while the internal voltage generator is not operating. The comparator further controls the resistor-voltage divider so that a current flows therethrough only when the internal voltage generator is operating.

摘要翻译： 内部电压发生器产生通过对外部电源电压进行上变频或下变频而获得的内部电压。 具有多个电阻器的电阻分压器输出通过根据电阻器的电阻比分压内部电压而获得的第一分压。 电容器分压器具有串联连接在内部电压发生器的输出端和地电平之间的多个电容器，从电容器输出第二分压。 比较器根据比较结果比较参考电压和用于控制内部电压发生器的第一分压。 比较器根据内部电压发生器运行时的参考电压与第一分压的比较结果，判定是否停止内部电压发生器的动作。 另一方面，比较器在内部电压发生器不工作时，基于参考电压和第二分压之间的比较结果来操作内部电压发生器。 比较器进一步控制电阻分压器，使得仅当内部电压发生器工作时，电流才流过。

公开(公告)号：US06240018B1

公开(公告)日：2001-05-29

申请号：US09451142

申请日：1999-11-30

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C1606

CPC分类号： G11C16/3459 ,  G11C7/1006 ,  G11C7/1048 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

摘要翻译： 一种非易失性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路，经由开关元件连接到触发器电路的位线，用于对位线充电的晶体管， 连接到位线并具有MOS晶体管结构的非易失性存储单元，用于当其阈值被设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，所述存储器单元的阈值为 当触发器电路保持在第一状态并且在触发器电路保持在第二状态时阈值的偏移不被影响，并且在验证时，从第一阈值范围向第二阈值范围移动 模式下，当阈值保持在第二阈值范围内时，位线由充电晶体管保持在充电电位，并且数据设置电路用于连接第一和第二信号节点之一 当位线在验证模式下处于电荷电位时，触发电路的电位达到预定电位，从而将触发器电路设置在第二状态，而与验证模式之前的状态无关。

公开(公告)号：US6002354A

公开(公告)日：1999-12-14

申请号：US166571

申请日：1998-10-06

申请人： Yasuo Itoh ,  Sumio Tanaka

发明人： Yasuo Itoh ,  Sumio Tanaka

IPC分类号： G11C16/06 ,  H03M1/68 ,  H03M1/74 ,  H03M1/76 ,  H03M1/78 ,  H03M1/66

CPC分类号： H03M1/68 ,  H03M1/785 ,  H03M1/76

摘要： A variable potential generating circuit includes a resistive potential divider circuit and first and second operational amplifiers. The resistive potential divider circuit includes a switching element and a current-scaling type digital/analog converter circuit connected in series between a power supply node and a ground node. The resistive potential divider circuit has a first node at which a divided potential obtained by resistive division of a variable potential to be output from a variable potential output node appears and a second node to which a virtual potential is applied. The first operational amplifier compares the divided potential of the first node with a reference potential to effect the feedback control for setting the variable output potential equal to the reference potential. The second operational amplifier compares the virtual potential of the second node with the reference potential to effect the feedback control for setting the virtual potential equal to the reference potential.

摘要翻译： 可变电位发生电路包括电阻分压器电路和第一和第二运算放大器。 电阻分压器电路包括在电源节点和接地节点之间串联连接的开关元件和电流调节型数字/模拟转换器电路。 电阻分压器电路具有第一节点，在该第一节点处出现通过对从可变电位输出节点输出的可变电位的电阻划分获得的分压电位和施加虚拟电位的第二节点。 第一运算放大器将第一节点的分压电位与参考电位进行比较，以实现用于设置等于参考电位的可变输出电位的反馈控制。 第二运算放大器将第二节点的虚拟电位与参考电位进行比较，以实现用于设置虚拟电位等于参考电位的反馈控制。

公开(公告)号：US5726882A

公开(公告)日：1998-03-10

申请号：US659229

申请日：1996-06-05

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，并且晶体管对位线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点之一连接到预定电位，从而将触发器电路设置为第二状态，而与 在验证模式之前的状态。

公开(公告)号：US5642072A

公开(公告)日：1997-06-24

申请号：US584732

申请日：1996-01-11

申请人： Junichi Miyamoto ,  Shigeru Atsumi ,  Yasuo Itoh

发明人： Junichi Miyamoto ,  Shigeru Atsumi ,  Yasuo Itoh

IPC分类号： G11C17/00 ,  G05F3/24 ,  G11C5/14 ,  G11C16/06 ,  H02M3/07 ,  G05F3/02

CPC分类号： G05F3/242 ,  G11C5/145 ,  H02M3/073

摘要： A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

摘要翻译： 高压发生器电路包括升压电路，限幅电路和旁路电路。 当电源电压输入到升压电路时，产生高电压并提供给限幅器电路。 当升压电路产生的高电压超过限制电路的限制电压时，限制电路工作，升压电路的输出电压因此维持在恒定值。 当输出电压超过限制电路的限制电压并且升压电路的输出电流超过参考值时，旁路与升压电路的输出电流的一部分相当于输出电流与预定值之间的差值， 由上述旁路电路放电。