公开(公告)号：US07194583B2

公开(公告)日：2007-03-20

申请号：US10464966

申请日：2003-06-19

申请人： Siegfried Kay Hesse ,  Dale E. Gulick

发明人： Siegfried Kay Hesse ,  Dale E. Gulick

IPC分类号： G06F12/00 ,  G06F12/12

CPC分类号： G06F12/121

摘要： A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.

摘要翻译： 提供了诸如南桥的USB主机控制器的主机控制器以及相应的操作方法。 主机控制器包括描述符提取单元，其适于发送对描述符的请求并且接收描述符以回复请求。 描述符是用于描述从主机控制器控制的设备传输数据的属性的数据结构。 主机控制器还包括适于存储预取描述符的描述符高速缓存。 所述描述符缓存进一步适于存储所存储的预取描述符的至少一部分的各个替换控制值。 主机控制器被设置为基于与所存储的预取描述符相关联的替换控制值，用新的预取描述符替换描述符高速缓存中存储的预取描述符。 替代技术可以提高主机控制器操作的整体效率。

公开(公告)号：US07146510B1

公开(公告)日：2006-12-05

申请号：US10198637

申请日：2002-07-18

申请人： Frank P. Helms ,  Derrick R. Meyer ,  Larry D. Hewitt ,  Dale E. Gulick ,  William A. Hughes ,  Scott E. Swanstrom

发明人： Frank P. Helms ,  Derrick R. Meyer ,  Larry D. Hewitt ,  Dale E. Gulick ,  William A. Hughes ,  Scott E. Swanstrom

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/172

摘要： An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.

摘要翻译： 集成电路耦合到通信链路和单独的信号线，并且包括指定通信链路宽度和频率的可编程寄存器。 通过将通信链路的至少一部分的宽度和/或频率响应于信号线的逻辑值的改变而改变为编程值，集成电路响应于信号线的值的变化，而没有 集成电路进入复位状态。 宽度和/或频率可以在POST程序期间或在系统操作期间作为功率管理或其他系统功能的一部分而改变，同时保持其操作状态。

公开(公告)号：US07003676B1

公开(公告)日：2006-02-21

申请号：US09871084

申请日：2001-05-30

申请人： Frederick D. Weber ,  Dale E. Gulick

发明人： Frederick D. Weber ,  Dale E. Gulick

IPC分类号： G06F11/30 ,  H04L9/00

CPC分类号： G06F21/82 ,  G06F21/74 ,  G06F21/79

摘要： A method and system for overriding access locks on secure assets in a computer system. The system includes a processor and a device coupled to the processor. The device includes one or more sub-devices, one or more access locks, and an access lock override register that stores one or more access lock override bits, including a lock override bit. The one or more access locks are configured to prevent access to the one or more sub-devices when the one or more access locks are engaged. Access to the one or more sub-devices is not allowed when the lock override bit is set. The method includes requesting a memory transaction for one or more memory addresses and determining a lock status for the one or more memory addresses. The method also includes returning the lock status for the one or more memory addresses. The method may determine if the lock status for the one or more memory address can be changed. The method may change the lock status of the one or more memory addresses to allow the memory transaction.

摘要翻译： 用于覆盖计算机系统中安全资产上的访问锁的方法和系统。 该系统包括处理器和耦合到处理器的设备。 该设备包括一个或多个子设备，一个或多个访问锁和存储一个或多个访问锁覆盖位的访问锁覆盖寄存器，其包括锁倍增位。 所述一个或多个访问锁被配置为当所述一个或多个访问锁定被接合时防止访问所述一个或多个子设备。 锁定倍率位置1时，不允许访问一个或多个子设备。 该方法包括为一个或多个存储器地址请求存储器事务并确定一个或多个存储器地址的锁定状态。 该方法还包括返回一个或多个存储器地址的锁定状态。 该方法可以确定一个或多个存储器地址的锁定状态是否可以改变。 该方法可以改变一个或多个存储器地址的锁定状态以允许存储器事务。

公开(公告)号：US06990550B2

公开(公告)日：2006-01-24

申请号：US10283555

申请日：2002-10-30

申请人： Siegfried Kay Hesse ,  Dale E. Gulick

发明人： Siegfried Kay Hesse ,  Dale E. Gulick

IPC分类号： G06F13/20 ,  H04J3/16

CPC分类号： G06F13/1605

摘要： A USB (Universal Serial Bus) host controller, a corresponding integrated circuit chip, a computer system and an operation method are provided for handling the data traffic between at least one USB device and the computer system having system memory. A transaction processing unit processes transactions to or from the at least one USB device. Further, a transaction duration management unit is provided for determining estimated duration values of the transactions. The transaction processing unit is adapted to process the transactions dependent on the estimated duration values. A descriptor-to-transaction converter may be provided, and the prefetched mechanism may be made dependent on a threshold value relating to the estimated duration values.

公开(公告)号：US06952751B1

公开(公告)日：2005-10-04

申请号：US09544858

申请日：2000-04-07

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F13/36 ,  G06F13/42 ,  H04Q1/30

CPC分类号： G06F13/4208

摘要： A method and system for operating a bus according to a plurality of bus protocols, including a legacy bus protocol. A first signal is transmitted indicating a transaction request of a first kind. A second signal is transmitted indicating a transaction request of a second kind. The second signal may be decoded according to a plurality of protocols. The first signal is decoded prior to decoding the second signal. The decode of the first signal indicates which of the plurality of protocols should be used to decode the second signal. A computer system includes a bus, preferably an LPC bus, coupling two or more devices.

摘要翻译： 一种用于根据包括传统总线协议的多个总线协议来操作总线的方法和系统。 发送指示第一类的交易请求的第一信号。 发送指示第二种类型的交易请求的第二信号。 可以根据多个协议对第二信号进行解码。 第一信号在解码第二信号之前被解码。 第一信号的解码指示应该使用多个协议来解码第二信号。 计算机系统包括耦合两个或多个设备的总线，优选地是LPC总线。

公开(公告)号：US06944725B2

公开(公告)日：2005-09-13

申请号：US10283733

申请日：2002-10-30

申请人： Siegfried Kay Hesse ,  Dale E. Gulick

发明人： Siegfried Kay Hesse ,  Dale E. Gulick

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F3/0601 ,  G06F2003/0691 ,  G06F2213/0042

摘要： A data storage mechanism is provided where a plurality of data items are stored in a plurality of register elements. Each registered element is capable of storing at least one data item. The plurality of register elements is arranged to form a sequence of register elements. First data is stored in a first part of the sequence and second data is stored in a second part of the sequence. The first part and the second part are of variable lengths with the sum of the variable lengths being equal to the lengths of the sequence of register elements. Thus, a double-ended queue mechanism is provided which may be used to store data of different type or data which is either scheduled periodically or asynchronously. The mechanism may be used in a USB 2.0 compliant host controller.

摘要翻译： 提供了一种数据存储机制，其中多个数据项被存储在多个寄存器元件中。 每个注册的元素能够存储至少一个数据项。 多个寄存器元件被布置成形成寄存器元件的序列。 第一数据存储在序列的第一部分中，第二数据被存储在序列的第二部分中。 第一部分和第二部分是可变长度，其可变长度之和等于寄存器元件序列的长度。 因此，提供了一种双端口队列机制，其可以用于存储周期性地或异步地调度的不同类型或数据的数据。 该机制可用于兼容USB 2.0的主机控制器。

公开(公告)号：US06836813B1

公开(公告)日：2004-12-28

申请号：US09998758

申请日：2001-11-30

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1336

CPC分类号： G06F13/4022 ,  G06F2213/0024 ,  G06F2213/0026

摘要： A switching I/O node for connection in a multiprocessor computer system. An input/output node switch includes a bridge unit and a packet bus switch unit implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link in response to determining the destination each of the upstream packet transactions.

摘要翻译： 用于在多处理器计算机系统中连接的交换I / O节点。 输入/输出节点开关包括在集成电路芯片上实现的桥单元和分组总线开关单元。 桥接单元可以从外围总线接收多个外围事务，并且可以发送与多个外围事务相对应的多个上行分组事务。 分组总线交换机可以在内部点对点分组总线链路上接收上行分组事务，并且可以确定每个上行分组事务的目的地。 分组总线交换机可以将上游分组事务中的选择的一个进一步路由到耦合到第一点对点分组总线链路的第一处理器接口，并将上游分组事务中的另一个路由到耦合到第二点到多个分组总线链路的第二处理器接口， 响应于确定每个上游分组事务的目的地，点对点分组总线链路。

公开(公告)号：US06823403B2

公开(公告)日：2004-11-23

申请号：US10184407

申请日：2002-06-27

申请人： Dale E. Gulick ,  Siegfried Kay Hesse

发明人： Dale E. Gulick ,  Siegfried Kay Hesse

IPC分类号： G06F1328

CPC分类号： G06F12/0879 ,  G06F13/28 ,  H04B7/0822

摘要： A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests for a memory interface and receiving requested data from the memory interface, comprises a data transfer initiating unit for outputting first address data identifying a first memory range. Further, a boundary alignment unit is provided for generating second address data using the first address data, where the second address data identifies a second memory range that differs from the first memory range in at least one boundary. Further a corresponding boundary alignment may be done in a receive DMA engine. The DMA mechanism may be performed in a USB-2 host controller that has HyperTransport capabilities.

摘要翻译： 提供了DMA（直接存储器访问）机制，其可以具有改进的性能，特别是与高速分组总线相关。 一种用于输出对存储器接口的读取请求并从存储器接口接收所请求的数据的发送DMA引擎，包括用于输出识别第一存储器范围的第一地址数据的数据传输启动单元。 此外，提供边界对齐单元，用于使用第一地址数据生成第二地址数据，其中第二地址数据标识与至少一个边界中的第一存储器范围不同的第二存储器范围。 此外，可以在接收DMA引擎中进行相应的边界对准。 DMA机制可以在具有HyperTransport功能的USB-2主机控制器中执行。

公开(公告)号：US06766347B1

公开(公告)日：2004-07-20

申请号：US09094168

申请日：1998-06-09

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F900

CPC分类号： G01R33/54

摘要： A computer system includes a real-time interrupt that causes the operating system to determine which isochronous tasks are pending. In one embodiment, applications that include isochronous tasks are certified to be well-behaved and the operating system will only initiate applications that are known to be well-behaved by checking a list of certified applications. The operating system will not initiate an application if insufficient resources are available for executing the tasks of the application. Each application informs the operating system of an execution rate and a maximum duration of its isochronous tasks. Prior to initiating an application, the operating system verifies that resources are available to execute the isochronous tasks of the application. The operating system includes a non-maskable interrupt to terminate isochronous tasks. Termination may be necessary if an isochronous task fails to execute within its specified maximum duration. Alternatively, an isochronous task may be preempted to execute a higher priority task. The operating system may include two types of time-slices. Higher priority tasks are allocated to quick slices and lower priority tasks are allocated to standard slices. Standard slices are preemptable and quick slices are not preemptable.

摘要翻译： 计算机系统包括使操作系统确定哪个等时任务正在等待的实时中断。 在一个实施例中，包括同步任务的应用被认证为良好的操作，并且操作系统将仅通过检查认证应用的列表来启动已知具有良好行为的应用。 如果没有足够的资源可用于执行应用程序的任务，操作系统将不会启动应用程序。 每个应用程序通知操作系统其同步任务的执行速率和最大持续时间。 在启动应用程序之前，操作系统会验​​证资源是否可用来执行应用程序的同步任务。 操作系统包括一个不可屏蔽的中断来终止同步任务。 如果同步任务在其指定的最大持续时间内无法执行，则可能需要终止。 或者，可以抢占同步任务来执行较高优先级的任务。 操作系统可以包括两种类型的时间片。 较高优先级的任务分配给快速切片，较低优先级的任务分配给标准切片。 标准切片是可抢占的，快速切片是不可抢占的。

公开(公告)号：US06697890B1

公开(公告)日：2004-02-24

申请号：US10034878

申请日：2001-12-27

申请人： Dale E. Gulick ,  Larry D. Hewitt

发明人： Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1312

CPC分类号： G06F13/4247 ,  G06F13/4004

摘要： An I/O node for a computer system including an integrated I/O interface. An input/output node for a computer system that is implemented upon an integrated circuit includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may receive and transmit packet transactions on a second link of the packet bus. The packet tunnel may convey selected packet transactions between the first and second transceiver units. The bridge unit may receive particular packet transactions from the first transceiver may transmit transactions corresponding to the particular packet transactions upon a peripheral bus. The I/O interface unit may receive additional packet transactions from the first transceiver unit and may transmit transactions corresponding to the additional packet transactions upon an I/O link.

摘要翻译： 一个包含集成I / O接口的计算机系统的I / O节点。 在集成电路上实现的用于计算机系统的输入/输出节点包括第一收发器单元，第二收发器单元，分组隧道，桥接单元和I / O接口单元。 第一收发器单元可以在分组总线的第一链路上接收和发送分组事务。 第二收发器单元可以在分组总线的第二链路上接收和发送分组事务。 分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。 桥接单元可以接收来自第一收发器的特定分组事务可以在外围总线上发送与特定分组事务相对应的事务。 I / O接口单元可以从第一收发器单元接收附加分组事务，并且可以在I / O链路上传送与附加分组事务相对应的事务。