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    METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    51.
    发明申请
    METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 有权

    公开(公告)号：US20210035617A1

    公开(公告)日：2021-02-04

    申请号：US16530739

    申请日：2019-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Eric J. Stave ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Chan H. Yoo ,  Randon K. Richards ,  Timothy M. Hollis

    IPC: G11C7/22 ,  G11C7/10 ,  G11C16/10

    Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES
    53.
    发明申请
    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES 审中-公开

    公开(公告)号：US20200321317A1

    公开(公告)日：2020-10-08

    申请号：US16905435

    申请日：2020-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

    MEMORY DEVICE INTERFACE AND METHOD
    54.
    发明申请
    MEMORY DEVICE INTERFACE AND METHOD 审中-公开

    公开(公告)号：US20200272564A1

    公开(公告)日：2020-08-27

    申请号：US16797571

    申请日：2020-02-21

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

    IPC: G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065

    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

    Dual sided fan-out package having low warpage across all temperatures
    55.
    发明授权
    Dual sided fan-out package having low warpage across all temperatures 有权

    公开(公告)号：US10714456B2

    公开(公告)日：2020-07-14

    申请号：US16379078

    申请日：2019-04-09

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

    Thrumold post package with reverse build up hybrid additive structure
    56.
    发明授权
    Thrumold post package with reverse build up hybrid additive structure 有权

    公开(公告)号：US10593568B2

    公开(公告)日：2020-03-17

    申请号：US16123158

    申请日：2018-09-06

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  John F. Kaeding ,  Ashok Pachamuthu ,  Mark E. Tuttle

    IPC: H01L21/56 ,  H01L23/31

    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.

    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES
    57.
    发明申请
    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES 审中-公开

    公开(公告)号：US20190237438A1

    公开(公告)日：2019-08-01

    申请号：US16379078

    申请日：2019-04-09

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00

    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

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