公开(公告)号：US11749316B2

公开(公告)日：2023-09-05

申请号：US17671000

申请日：2022-02-14

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C7/00 ,  G11C5/14 ,  G06F13/16 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

CPC classification number: G11C5/144 ,  G06F13/1668 ,  G11C5/14 ,  G11C5/142 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30 ,  Y02D10/00

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

公开(公告)号：US20230176747A1

公开(公告)日：2023-06-08

申请号：US17684112

申请日：2022-03-01

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/065 ,  G06F3/0679

Abstract: A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.

公开(公告)号：US20230097079A1

公开(公告)日：2023-03-30

申请号：US16976411

申请日：2020-05-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Stefan Frederik Schippers ,  Efrem Bolandrina

IPC: H01L27/24 ,  G11C13/00

Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

公开(公告)号：US20230005533A1

公开(公告)日：2023-01-05

申请号：US17364067

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C13/00

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

公开(公告)号：US20220399055A1

公开(公告)日：2022-12-15

申请号：US17864004

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

IPC: G11C13/00

Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

公开(公告)号：US20220366983A1

公开(公告)日：2022-11-17

申请号：US17597816

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Stefan Frederik Schippers ,  Lorenzo Fratin

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10

Abstract: The present disclosure provides a memory apparatus and a method for accessing a 3D vertical memory array. The 3D vertical memory array comprises word lines organized in planes separated from each other by insulating material, bit lines perpendicular to the word line planes, memory cells coupled between a respective word line and a respective bit line. The apparatus also comprises a controller configured to select multiple word lines, select multiple bit lines, and simultaneously access multiple memory cells, with each memory cell at a crossing of a selected word line and a selected bit line. The method comprises selecting a multiple word lines, selecting multiple bit lines and simultaneously accessing multiple memory cells, with each memory cell at a crossing of a selected word line of the selected multiple word lines and a selected bit line of the selected multiple bit lines. A method of manufacturing a 3D vertical memory array is also described.

公开(公告)号：US11437097B2

公开(公告)日：2022-09-06

申请号：US17116893

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Ferdinando Bedeschi ,  Paolo Fantini

IPC: G11C13/00 ,  H01L45/00

Abstract: Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).

公开(公告)号：US20220230668A1

公开(公告)日：2022-07-21

申请号：US17590528

申请日：2022-02-01

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa

IPC: G11C8/16

Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

公开(公告)号：US10998074B2

公开(公告)日：2021-05-04

申请号：US16518824

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Shane D. Moser

IPC: G11C11/408 ,  G11C16/04 ,  G11C29/18 ,  G11C11/419 ,  G11C11/22 ,  G11C13/00

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

公开(公告)号：US20200160898A1

公开(公告)日：2020-05-21

申请号：US16748671

申请日：2020-01-21

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa

IPC: G11C8/16

Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.