公开(公告)号：US10825494B2

公开(公告)日：2020-11-03

申请号：US16683018

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C8/10 ,  G11C11/4096 ,  H04L25/03 ,  G06F13/18 ,  G11C11/4074

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.

公开(公告)号：US10825491B2

公开(公告)日：2020-11-03

申请号：US15837666

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Gary L. Howe ,  Harish N. Venkata ,  David R. Brown

IPC: G11C7/10 ,  G11C11/4072 ,  G11C8/04 ,  G11C11/408 ,  G11C7/20 ,  G06F12/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/02 ,  G11C29/46

Abstract: A memory device may include a memory array, which may also include, multiple memory cells. The memory device may also include one or more counters designed to generate internal memory addresses to sequentially access the memory cells and facilitate writing logical zeros to all of the memory cells.

公开(公告)号：US10817569B2

公开(公告)日：2020-10-27

申请号：US15806073

申请日：2017-11-07

Applicant: Micron Technology Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F16/903 ,  G06F11/30

Abstract: Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor may control the saving of state variables from the state variable array to the state variable storage array. The state variable storage control logic may also control restoring of the state variables from the state variable storage array to restore a search state.

公开(公告)号：US10671295B2

公开(公告)日：2020-06-02

申请号：US16694584

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F9/312 ,  G06F3/06 ,  G06N3/02 ,  G06F8/41

Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

公开(公告)号：US20200133893A1

公开(公告)日：2020-04-30

申请号：US16726523

申请日：2019-12-24

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US10372653B2

公开(公告)日：2019-08-06

申请号：US16053562

申请日：2018-08-02

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit S. Bains

IPC: G06F15/18 ,  G06F13/40 ,  G06F15/78 ,  G06F9/448 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

公开(公告)号：US20190235766A1

公开(公告)日：2019-08-01

申请号：US16376881

申请日：2019-04-05

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F3/06 ,  G06N3/02 ,  G06F8/41

CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0664 ,  G06F3/0673 ,  G06F8/42 ,  G06N3/02

Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

公开(公告)号：US20190179552A1

公开(公告)日：2019-06-13

申请号：US15837666

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Gary L. Howe ,  Harish N. Venkata ,  David R. Brown

IPC: G06F3/06 ,  G11C11/4072 ,  G11C11/4091

Abstract: A memory device may include a memory array, which may also include, multiple memory cells. The memory device may also include one or more counters designed to generate internal memory addresses to sequentially access the memory cells and facilitate writing logical zeros to all of the memory cells.

公开(公告)号：US10254976B2

公开(公告)日：2019-04-09

申请号：US15206824

申请日：2016-07-11

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F9/312 ,  G06F3/06 ,  G06F8/41 ,  G06N3/02

Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

公开(公告)号：US20190050284A1

公开(公告)日：2019-02-14

申请号：US15674178

申请日：2017-08-10

Applicant: Micron Technology, Inc.

Inventor： David R. Brown

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1044 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/106 ,  G06F12/00

Abstract: As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of a memory array. To facilitate this functionality, a command controller may be provided, including one or more individual controllers to control the address sequencing when a particular mode entry command (e.g., Fast Zero or ECS) is received. In order to generate internal addresses to be accessed sequentially, one or more counters may also be provided. Advantageously, the counters may be shared such that they can be used in any mode of operation that may require address sequencing of all or large portions of the memory array, such as the Fast Zero mode or the ECS mode.