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公开(公告)号:US10381101B2
公开(公告)日:2019-08-13
申请号:US15849262
申请日:2017-12-20
Applicant: Micron Technology, Inc.
Inventor: Amitava Majumdar , Rajesh Kamana , Hongmei Wang , Shawn D. Lyonsmith , Ervin T. Hill , Zengtao T. Liu , Marlon W. Hug
Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.
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公开(公告)号:US20190189209A1
公开(公告)日:2019-06-20
申请号:US15918662
申请日:2018-03-12
Applicant: Micron Technology, Inc.
Inventor: Amitava Majumdar , Rajesh Kamana , Hongmei Wang , Shawn D. Lyonsmith , Ervin T. Hill , Zengtao T. Liu , Marlon W. Hug
CPC classification number: G11C13/048 , G11C7/005 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C29/02 , G11C29/025 , G11C29/50004 , G11C29/56008 , G11C29/56016 , G11C2029/5602 , G11C2213/76
Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.
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公开(公告)号:US09196357B2
公开(公告)日:2015-11-24
申请号:US14137189
申请日:2013-12-20
Applicant: Micron Technology, Inc.
Inventor: Karthik Sarpatwari , Hongmei Wang , Rangan Sanjay
CPC classification number: G11C13/0038 , G11C7/02 , G11C7/12 , G11C8/08 , G11C11/1673 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/005 , G11C2213/72 , G11C2213/76
Abstract: Voltage balancing for a memory cell array is provided. One example method of voltage balancing for a memory array can include activating an access node coupled to a row of a memory array to provide voltage to the row of the memory array, activating a stabilizing transistor coupled to the row of the memory array to create a feedback loop, and activating a driving node coupled to a column of the memory array, wherein activating the driving node deactivates the stabilizing transistor once the column reaches a particular voltage potential.
Abstract translation: 提供了存储单元阵列的电压平衡。 用于存储器阵列的电压平衡的一个示例性方法可以包括激活耦合到存储器阵列的接入节点以向存储器阵列的行提供电压,激活耦合到存储器阵列的稳定晶体管以产生 反馈回路,以及激活耦合到存储器阵列的列的驱动节点,其中一旦列达到特定电压电位,激活驱动节点就使稳定晶体管去激活。
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