公开(公告)号：US6036875A

公开(公告)日：2000-03-14

申请号：US802738

申请日：1997-02-20

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/033 ,  H01L21/3213 ,  C23F1/00

CPC classification number: H01L21/0338 ,  H01L21/32139

Abstract: A method for ultra-fine patterning of a semiconductor device performs a first, anisotropic etching of a hard mask layer according to a pattern created by lithographic techniques to create lines in the hard mask layer having an initial width. A second, anisotropic etching is performed on the hard mask layer to narrow the lines further than otherwise possible with a single etching according to the patterns created by lithography. Using the narrowed lines created in the hard mask layer, a third, anisotropic etching is performed, this time on the conductor layer shadowed by the narrow lines of the hard mask layer. The third etching creates narrow lines in the conductor layer in accordance with the narrow lines of the hard mask layer.

Abstract translation: 半导体器件的超精细图案化方法根据由光刻技术产生的图案对硬掩模层进行第一次各向异性蚀刻，以在具有初始宽度的硬掩模层中产生线。 第二，在硬掩模层上执行各向异性蚀刻，以根据通过光刻产生的图案，通过单次蚀刻而使线更窄。 使用在硬掩模层中产生的窄线，进行第三次各向异性蚀刻，此时在由硬掩模层的窄线遮蔽的导体层上。 第三蚀刻根据硬掩模层的窄线在导体层中产生窄线。

公开(公告)号：US5937319A

公开(公告)日：1999-08-10

申请号：US961828

申请日：1997-10-31

Applicant: Qi Xiang ,  Subash Gupta ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Subash Gupta ,  Ming-Ren Lin

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/336

CPC classification number: H01L21/28123

Abstract: A method of fabricating a polysilicon gate 8 in a metal oxide semiconductor (MOS) transistor in an integrated circuit includes providing a metal layer 18, such as cobalt, on the sidewall 12 of the polysilicon gate 8, silicidizing the metal with the polysilicon in the polysilicon gate 8 to form a metal silicide sidewall 20, and removing the metal silicide sidewall 20 by etching.

Abstract translation: 在集成电路中的金属氧化物半导体（MOS）晶体管中制造多晶硅栅极8的方法包括在多晶硅栅极8的侧壁12上提供诸如钴的金属层18，在金属氧化物半导体 多晶硅栅极8以形成金属硅化物侧壁20，并通过蚀刻去除金属硅化物侧壁20。

公开(公告)号：US5639691A

公开(公告)日：1997-06-17

申请号：US590781

申请日：1996-01-24

Applicant: Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/283

CPC classification number: H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

公开(公告)号：US07078278B2

公开(公告)日：2006-07-18

申请号：US10833073

申请日：2004-04-28

Applicant: James Pan ,  Ming-Ren Lin

Inventor： James Pan ,  Ming-Ren Lin

IPC: H01L28/80

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823842

Abstract: A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region. The first silicide region of the NMOS gate electrode consists of a first silicide having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region on the substrate and a second metal region on the second silicide region. The second silicide region of the PMOS gate electrode consists of a second silicide having a work function that is close to the valence band of silicon.

Abstract translation: 双金属CMOS布置及其制造方法提供了形成在衬底上的衬底和多个NMOS器件和PMOS器件。 多个NMOS器件和PMOS器件中的每一个具有栅电极。 每个NMOS栅极包括衬底上的第一硅化物区域和第一硅化物区域上的第一金属区域。 NMOS栅电极的第一硅化物区域由具有接近硅导带的功函数的第一硅化物组成。 每个PMOS栅极电极包括衬底上的第二硅化物区域和第二硅化物区域上的第二金属区域。 PMOS栅电极的第二硅化物区域由具有接近硅的价带的功函数的第二硅化物组成。

公开(公告)号：US20050245016A1

公开(公告)日：2005-11-03

申请号：US10833073

申请日：2004-04-28

Applicant: James Pan ,  Ming-Ren Lin

Inventor： James Pan ,  Ming-Ren Lin

IPC: H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823842

Abstract: A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region. The first silicide region of the NMOS gate electrode consists of a first silicide having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region on the substrate and a second metal region on the second silicide region. The second silicide region of the PMOS gate electrode consists of a second silicide having a work function that is close to the valence band of silicon.

Abstract translation: 双金属CMOS布置及其制造方法提供了形成在衬底上的衬底和多个NMOS器件和PMOS器件。 多个NMOS器件和PMOS器件中的每一个具有栅电极。 每个NMOS栅极包括衬底上的第一硅化物区域和第一硅化物区域上的第一金属区域。 NMOS栅电极的第一硅化物区域由具有接近硅导带的功函数的第一硅化物组成。 每个PMOS栅极电极包括衬底上的第二硅化物区域和第二硅化物区域上的第二金属区域。 PMOS栅电极的第二硅化物区域由具有接近硅的价带的功函数的第二硅化物组成。

公开(公告)号：US06833587B1

公开(公告)日：2004-12-21

申请号：US10174328

申请日：2002-06-18

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L2701

CPC classification number: H01L21/76256 ,  H01L21/84 ,  Y10S438/928

Abstract: A silicon-on-insulator substrate is disclosed which comprises: a silicon substrate layer; a first insulation layer over the silicon substrate layer; a conductive layer over the first insulation layer comprising at least one metal or metal silicide over the first insulation layer; a second insulation layer over the conductive layer; a silicon device layer comprising silicon over the second insulation layer; and at least one conductive plug through the silicon substrate layer and the first insulation layer contacting the conductive layer, or at least one conductive plug through the silicon device layer and the second insulation layer contacting the conductive layer. Also disclosed are methods for making silicon-on-insulator substrates having improved heat transfer structures.

Abstract translation: 公开了一种绝缘体上硅衬底，其包括：硅衬底层; 硅衬底层上的第一绝缘层; 所述第一绝缘层上的导电层包括在所述第一绝缘层上的至少一种金属或金属硅化物; 导电层上的第二绝缘层; 在第二绝缘层上包含硅的硅器件层; 以及穿过所述硅衬底层和所述第一绝缘层接触所述导电层的至少一个导电插塞，或通过所述硅器件层和所述第二绝缘层接触所述导电层的至少一个导电插塞。 还公开了制造具有改进的传热结构的绝缘体上硅衬底的方法。

公开(公告)号：US06531753B1

公开(公告)日：2003-03-11

申请号：US10174046

申请日：2002-06-18

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L2912

CPC classification number: H01L21/76251

Abstract: A silicon-on-insulator substrate is disclosed which comprises: a silicon substrate layer; a first insulation layer over the silicon substrate layer; a conductive layer over the first insulation layer comprising at least one metal or metal silicide over the first insulation layer; a second insulation layer over the conductive layer; a silicon device layer comprising silicon over the second insulation layer; at least first conductive plug through the silicon substrate and the first insulation layer contacting the conductive layer; and at least one second conductive plug through the silicon device layer and the second insulation layer contacting the conductive layer. Also disclosed are methods for forming silicon-on-insulator substrates having improved stable ground characteristics.

Abstract translation: 公开了一种绝缘体上硅衬底，其包括：硅衬底层; 硅衬底层上的第一绝缘层; 所述第一绝缘层上的导电层包括在所述第一绝缘层上的至少一种金属或金属硅化物; 导电层上的第二绝缘层; 在第二绝缘层上包含硅的硅器件层; 穿过硅衬底的至少第一导电插塞和与导电层接触的第一绝缘层; 以及穿过所述硅器件层和所述第二绝缘层接触所述导电层的至少一个第二导电插塞。 还公开了用于形成具有改进的稳定接地特性的绝缘体上硅衬底的方法。

公开(公告)号：US06486038B1

公开(公告)日：2002-11-26

申请号：US09804360

申请日：2001-03-12

Applicant: Witold P. Maszara ,  Ming-Ren Lin ,  Qi Xiang

Inventor： Witold P. Maszara ,  Ming-Ren Lin ,  Qi Xiang

IPC: H01L2176

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of (a) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; (b) etching the silicon active layer to form an isolation trench wherein an unetched silicon layer at bottom of the isolation trench remains; (c) oxidizing the layer of silicon at the bottom of the isolation trench to a degree sufficient to oxidize through the layer of silicon at the bottom to the dielectric isolation layer; and (d) filling the isolation trench with a trench isolation material to form a shallow trench isolation structure.

Abstract translation: 一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：（a）提供具有硅有源层，介电隔离层和硅衬底的绝缘体上硅半导体晶片，其中 在介电隔离层上形成硅有源层，并在硅衬底上形成电介质隔离层; （b）蚀刻硅有源层以形成隔离沟槽，其中保留隔离沟槽底部的未蚀刻硅层; （c）将隔离沟槽的底部的硅层氧化至足以通过底部的硅层氧化成电介质隔离层的程度; 和（d）用沟槽隔离材料填充隔离沟槽以形成浅沟槽隔离结构。

公开(公告)号：US06483147B1

公开(公告)日：2002-11-19

申请号：US09427135

申请日：1999-10-25

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L2701

CPC classification number: H01L21/743 ,  H01L21/84 ,  H01L23/3677 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, the present invention relates to a method of facilitating heat removal from a device layer of a silicon-on-insulator substrate comprising bulk silicon, an insulation layer over the bulk silicon, and a silicon device layer over the insulation layer involving forming at least one conductive plug comprising a conductive material within the bulk silicon and the insulation layer so as to contact the silicon device layer. In another embodiment, the present invention relates to a silicon-on-insulator structure, made of a silicon substrate layer; an insulation layer over the silicon substrate layer; a silicon device layer comprising silicon over the insulation layer; a conductive plug through the silicon substrate layer and the insulation layer contacting the silicon device layer; and a heat generating structure on the silicon device layer at least partially overlapping the conductive plug.

Abstract translation: 在一个实施例中，本发明涉及一种促进从绝缘体上硅衬底的器件层的散热的方法，其包括体硅，体硅上的绝缘层和绝缘层上的硅器件层，包括形成 至少一个导电插塞，其包括本体硅内的导电材料和绝缘层，以便与硅器件层接触。 在另一个实施例中，本发明涉及由硅衬底层制成的绝缘体上硅结构; 硅衬底层上的绝缘层; 在所述绝缘层上包含硅的硅器件层; 穿过硅衬底层的导电插塞和与硅器件层接触的绝缘层; 以及在硅器件层上的至少部分地与导电插塞重叠的发热结构。

公开(公告)号：US06274420B1

公开(公告)日：2001-08-14

申请号：US09510786

申请日：2000-02-23

Applicant: Qi Xiang ,  Wei Long ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC: H01L218238

CPC classification number: H01L29/665 ,  H01L21/76224

Abstract: STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches. The present invention may be used to particular advantage when the first dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the second dielectric material deposited on the sidewalls of the first dielectric material is comprised of silicon nitride. With the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.

Abstract translation: 制造STI（浅沟槽隔离）结构，使得通过在STI结构之间制造的场效应晶体管使漏电流最小化。 浅沟槽隔离结构包括一对隔离沟槽，每个隔离沟槽通过半导体衬底被蚀刻。 第一介电材料填充一对隔离沟槽并从隔离沟槽延伸，使得填充隔离沟槽的第一介电材料的侧壁暴露在半导体衬底的顶部之外。 第二电介质材料沉积在暴露于半导体衬底的顶部之外的第一电介质材料的侧壁上。 第二电介质材料在从填充隔离沟槽的第一介电材料的酸性溶液中具有不同的蚀刻速率。 当填充隔离沟槽的第一介电材料由二氧化硅组成并且当沉积在第一介电材料的侧壁上的第二介电材料由氮化硅构成时，本发明可以被用于特别有利。 通过覆盖填充STI（浅沟槽隔离）沟槽的二氧化硅的侧壁的保护性氮化硅，在填充STI（浅沟槽隔离）沟槽的二氧化硅中避免形成纹理。 因此，当在这样的STI结构之间制造场效应晶体管时，形成在STI结构附近的硅化物不会朝向场效应晶体管的漏极接触区域和源极接触区域的接点向下延伸，使得漏极和漏极电流为 最小化。