公开(公告)号：US20070206421A1

公开(公告)日：2007-09-06

申请号：US11384057

申请日：2006-03-17

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5642 ,  G11C16/0483

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.

摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 在不同时间编程的相邻存储器单元组之间最明显地出现该问题。 为了解决这种耦合，特定存储器单元的读取过程将向相邻存储器单元提供补偿，以便减少相邻存储单元对特定存储单元具有的耦合效应。

公开(公告)号：US20070147113A1

公开(公告)日：2007-06-28

申请号：US11321996

申请日：2005-12-28

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/28

摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

摘要翻译： 本发明提供了一种用于感测存储器单元的方案。 所选择的存储单元通过其通道放电到地，然后将电压电平放置在传统源上，并将另一个电压电平放置在控制栅上，并允许单元位线充电。 存储单元的位线然后将充电直到位线电压变得足够高以截止任何进一步的单元导通。 位线电压的升高将以一定的速率发生，并且取决于单元的数据状态，并且当位线达到足够高的电平时，单元将关闭，使得体效应影响存储单元阈值 到达目前，当前基本上关闭。 特定实施例执行多个这样的感测子操作，每个具有不同的控制栅极电压，但是在每个操作中通过对先前放电的单元通过其源极充电来感测多个状态。

公开(公告)号：US20070023838A1

公开(公告)日：2007-02-01

申请号：US11540262

申请日：2006-09-29

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L27/12

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material and a second layer of conductive material. The first layer may include a first gate region and a first interconnect region, and the second layer of conductive material may include a second gate region and a second interconnect region. It will be appreciated that the various techniques described herein for using multiple layers of conductive material to form interconnect regions and/or gate regions of memory cells provides extra degrees of freedom in fine tuning memory cell parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

摘要翻译： 各种实施例涉及与诸如静态随机存取存储器（SRAM）单元等存储单元的设计和实现有关的不同方法和系统。 在一个实施例中，存储单元可以包括第一导电材料层和第二导电材料层。 第一层可以包括第一栅极区和第一互连区，并且第二层导电材料可以包括第二栅极区和第二互连区。 应当理解，本文描述的用于使用多层导电材料形成存储器单元的互连区域和/或栅极区域的各种技术在微调存储器单元参数中提供了额外的自由度，例如，氧化物厚度，阈值 电压，最大允许栅极电压等

公开(公告)号：US20060221700A1

公开(公告)日：2006-10-05

申请号：US11429769

申请日：2006-05-08

申请人： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

发明人： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5624

摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

摘要翻译： 通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。 通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。 精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

公开(公告)号：US07113432B2

公开(公告)日：2006-09-26

申请号：US10718454

申请日：2003-11-19

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/16 ,  G11C16/3495

摘要： A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. Complementary embodiments include updating the compressed count based upon a random number or upon the actual count matching a multiple of the fixed number. These techniques also have application to monitoring other types of recurring events in flash memory systems or in other types of electronic systems. In another aspect of the present invention, provisions are made to maintain an accurate experience count if the memory system experiences an improper shutdown, for example in case of power loss or removal of a memory card.

摘要翻译： 非易失性闪速存储器系统通过仅针对大量这种事件的发生更新一次压缩计数来计数事件的发生，例如各个块已被擦除和重写的次数。 互补实施例包括基于随机数更新压缩计数，或者根据实际计数匹配固定数量的倍数。 这些技术还可用于监视闪存系统或其他类型的电子系统中的其他类型的重复事件。 在本发明的另一方面，如果存储器系统经历不正常的关机，例如在电源丢失或存储卡的移除的情况下，则提供保持准确的体验计数。

公开(公告)号：US07068539B2

公开(公告)日：2006-06-27

申请号：US10766116

申请日：2004-01-27

申请人： Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

发明人： Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5624

摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

公开(公告)号：US20050248988A1

公开(公告)日：2005-11-10

申请号：US10839764

申请日：2004-05-05

申请人： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

发明人： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/12 ,  G11C16/30 ,  G11C16/34

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C16/3459

摘要： A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings while applying the first phase of the boosting signal, and applying an inhibit level to unselected bit lines of the NAND strings while applying the first phase of the boosting signal. Subsequently, a second phase of the boosting signal is applied to the one or more unselected word lines and the signal(s) on the selected bit lines are changed by applying the inhibit level to the selected bit lines so that NAND strings associated with the selected bit lines will be boosted by the second phase of the boosting signal. A program voltage signal is applied to a selected word line in order to program storage elements connected to the selected word line.

摘要翻译： 公开了一种更精确地编程非易失性存储器的系统。 在一个实施例中，该系统包括将一个升压信号的第一相位应用于一组NAND串的一个或多个未选字线，将编程电平施加到NAND串的选定位线，同时施加升压信号的第一相位 并且在施加升压信号的第一相位时将禁止电平施加到NAND串的未选位线。 随后，将升压信号的第二相位施加到一个或多个未选字线，并且通过将所述禁止电平施加到所选择的位线来改变所选位线上的信号，使得与所选择的位线相关联的NAND串 位线将由升压信号的第二阶段提升。 将程序电压信号施加到所选择的字线，以便编程连接到所选字线的存储元件。

公开(公告)号：US20050157549A1

公开(公告)日：2005-07-21

申请号：US10762181

申请日：2004-01-21

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.

摘要翻译： 非易失性存储器件在源极/漏极区域之间具有沟道区域，浮置栅极，控制栅极，沟道区域和浮置栅极之间的第一介电区域以及浮置栅极和控制栅极之间的第二介电区域 。 第一电介质区域包括高K材料。 通过经由第二电介质区域在浮动栅极和控制栅极之间传送电荷来对非易失性存储器件进行编程和/或擦除。

公开(公告)号：US06850441B2

公开(公告)日：2005-02-01

申请号：US10052924

申请日：2002-01-18

申请人： Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

发明人： Nima Mokhlesi ,  Daniel C. Guterman ,  Geoffrey S. Gongwer

IPC分类号： G11C16/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C11/5642 ,  G11C16/0458 ,  G11C16/26

摘要： The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

摘要翻译： 本发明提供了用于通过在读取过程的一部分中对电池的一些或多个端子施加情景搅动（例如，时变电压）来减少读取非易失性存储装置中固有噪声的量的方法。 本发明的各个方面也扩展到超出非易失性存储器的设备。 根据本发明的一个方面，除了作为读取过程的一部分而施加到单元的正常电压电平之外，还对电池施加时变电压。 一组示例性实施例在读取过程的信号积分时间之前或期间将单个或多组交流电应用于浮动栅极存储器单元的一个或多个端子。 在其他实施例中，可重复的其他可再现的外部或内部搅拌以及其平均效应（从一个积分时间到下一个积分时间）保持足够恒定，以便具有净噪声降低效果。

公开(公告)号：US08472255B2

公开(公告)日：2013-06-25

申请号：US13605714

申请日：2012-09-06

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。