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    Specifying a 3-phase or N-phase eye pattern
    51.
    发明授权
    Specifying a 3-phase or N-phase eye pattern 有权
    指定3相或N相眼图

    公开(公告)号：US09215063B2

    公开(公告)日：2015-12-15

    申请号：US14507702

    申请日：2014-10-06

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley ,  Chulkyu Lee

    IPC: H04L7/04 ,  H04L1/20 ,  H04L1/24 ,  H04L25/49 ,  H04L25/02 ,  H04L5/20

    CPC classification number: H04L7/042 ,  H04L1/205 ,  H04L1/206 ,  H04L1/247 ,  H04L5/20 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L25/4917

    Abstract: System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols may be generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities.

    Abstract translation: 描述了便于与多线，多相通信链路相关的测试和测量的系统，方法和装置。 信息以N相极性编码符号发送，并且可以生成与符号相对应的眼图，使得符号与对应于用于采样符号的时钟边缘的每个符号的触发对齐。 眼图可以用于确定通信链路中的建立时间的充分性以及定义通信信道能力的其它这样的特性。

    MULTIPOINT INTERFACE SHORTEST PULSE WIDTH PRIORITY RESOLUTION
    53.
    发明申请
    MULTIPOINT INTERFACE SHORTEST PULSE WIDTH PRIORITY RESOLUTION 有权
    多点接口最佳脉冲宽度优先级分辨率

    公开(公告)号：US20150146624A1

    公开(公告)日：2015-05-28

    申请号：US14089550

    申请日：2013-11-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： George Alan Wiley ,  Olaf Josef Hirsch ,  Richard Dominic Wietfeldt

    IPC: H04W52/18 ,  H04W52/54 ,  H04W88/02

    CPC classification number: H04W52/18 ,  H04L12/4015 ,  H04L12/413 ,  H04W52/54 ,  H04W88/02

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Each device can contend for control of a communications link by driving a data signal to a first voltage level. If the data signal or a clock signal changes before an arbitration time period has elapsed, one or more devices yield control of the communications link to another contender. The arbitration time period for each contender is different and indicates a priority of the message to be transmitted. A shorter arbitration time period indicates higher priority. Arbitration may commence after clock and data signals of the communications link remain in an idle or other predefined state for a minimum idle time. The minimum idle time may be different for different nodes and may be shorter for high priority messages or nodes.

    Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 每个设备可以通过将数据信号驱动到第一电压电平来争取控制通信链路。 如果在仲裁时间段过去之前数据信号或时钟信号改变，则一个或多个设备产生对另一个竞争者的通信链路的控制。 每个竞争者的仲裁时间段不同，表示要发送的消息的优先级。 较短的仲裁时间段表示优先级较高。 仲裁可以在通信链路的时钟和数据信号保持在空闲或其他预定义状态中达到最小空闲时间之后开始。 不同节点的最小空闲时间可能不同，对于高优先级消息或节点可能较短。

    N-PHASE SIGNAL TRANSITION ALIGNMENT
    55.
    发明申请
    N-PHASE SIGNAL TRANSITION ALIGNMENT 有权
    N相信号转换对准

    公开(公告)号：US20150043693A1

    公开(公告)日：2015-02-12

    申请号：US14453346

    申请日：2014-08-06

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  George Alan Wiley

    IPC: H04L7/00

    CPC classification number: G06F13/36 ,  G06F13/4063 ,  G06F13/4068 ,  G06F13/4278 ,  G06F13/4282 ,  H04L7/0033 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/4919 ,  Y02D10/14 ,  Y02D10/151

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.

    Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 驱动器可以被适配或配置成在两个或更多个连接器上对准状态转换，以使连续符号之间的过渡周期最小化。 驱动器可以包括推进或延迟某些转换的电路。 驱动器可以包括预加重电路，即，即使当连接器转换到未驱动状态时，该预加重电路用于驱动连接器的一部分过渡期的状态。

    RUN-LENGTH DETECTION AND CORRECTION
    56.
    发明申请
    RUN-LENGTH DETECTION AND CORRECTION 有权
    运行长度检测和校正

    公开(公告)号：US20150043358A1

    公开(公告)日：2015-02-12

    申请号：US14453287

    申请日：2014-08-06

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley ,  Chulkyu Lee

    IPC: H04L1/00 ,  H04L12/26

    CPC classification number: H04L1/0056 ,  H04L1/0014 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L43/0811

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. The apparatus may determine whether a run-length violation will occur or is likely to occur if a first sequence of symbols provided by a mapper of an M-Wire N-Phase encoder is transmitted on a plurality of wires. A second sequence of symbols may be substituted for the first sequence of symbols. The second sequence of symbols may comprise a surplus sequence of symbols that is not used for mapping data in the mapper.

    Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 如果由M-Wire N相编码器的映射器提供的第一符号序列在多个导线上传输，则装置可以确定是否会发生游程长度违规或可能发生游程长度违例。 符号的第二序列可以代替第一符号序列。 第二符号序列可以包括不用于映射器中的数据的多余符号序列。

    MULTI-WIRE SINGLE-ENDED PUSH-PULL LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING
    57.
    发明申请
    MULTI-WIRE SINGLE-ENDED PUSH-PULL LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING 有权
    带数据符号转换的多线单向推拉链接

    公开(公告)号：US20140270026A1

    公开(公告)日：2014-09-18

    申请号：US14205242

    申请日：2014-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

    IPC: H04L7/027

    CPC classification number: H04L7/027 ,  G06F13/4072 ,  G06F13/4295 ,  H04L25/00 ,  H04L25/14

    Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

    Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 数据比特序列被转换成M个转换号码，然后转换成符号序列。 通过N线接收符号序列。 可以有效地将时钟信号嵌入到符号序列的传输中。 符号序列中的每一个可以基于M个转移号码中的一个和符号序列中的前一个的值来选择。

    THREE PHASE AND POLARITY ENCODED SERIAL INTERFACE
    58.
    发明申请
    THREE PHASE AND POLARITY ENCODED SERIAL INTERFACE 有权

    公开(公告)号：US20130215991A1

    公开(公告)日：2013-08-22

    申请号：US13826546

    申请日：2013-03-14

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley

    IPC: H04L25/49

    CPC classification number: H04L25/4917 ,  H04L5/20 ,  H04L7/033 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L27/22

    Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

    Reducing transmitter encoding jitter in a C-PHY interface using multiple clock phases to launch symbols
    60.
    发明授权
    Reducing transmitter encoding jitter in a C-PHY interface using multiple clock phases to launch symbols 有权

    公开(公告)号：US10289600B2

    公开(公告)日：2019-05-14

    申请号：US15332756

    申请日：2016-10-24

    Applicant: QUALCOMM Incorporated

    Inventor： Dhaval Sejpal ,  Shih-Wei Chou ,  Chulkyu Lee ,  Ohjoon Kwon ,  George Alan Wiley

    IPC: G06F13/20 ,  G06F13/42 ,  H04L25/49 ,  H04L7/00

    Abstract: A method for error detection in transmissions on a multi-wire interface includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.

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