公开(公告)号：US20230246002A1

公开(公告)日：2023-08-03

申请号：US18059646

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi YANAGIGAWA ,  Kazuhisa MORI ,  Toshiyuki HATA

IPC: H01L25/07 ,  H01L23/00 ,  H01L29/78

CPC classification number: H01L25/074 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L29/7805 ,  H01L29/7813 ,  H01L2224/32145 ,  H01L2224/40227 ,  H01L2224/73263 ,  H01L2924/13091 ,  H02M7/537

Abstract: A semiconductor device includes: a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode; and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed in a first front surface of the first semiconductor chip, and a first drain electrode is formed in a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed in a second front surface of the second semiconductor chip, and a second drain electrode is formed in a second back surface of the second semiconductor chip. The first front surface and the second front surface face each other such that the first source electrode and the second source electrode are in contact with each other via a conductive paste.

公开(公告)号：US20230039359A1

公开(公告)日：2023-02-09

申请号：US17838707

申请日：2022-06-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Masami SAWADA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/66

Abstract: Variations of characteristics of a semiconductor device provided with a power MOSFET having a super junction structure are suppressed, and reliability of the semiconductor device is improved. A trench embedding an insulating film, which constitutes an insulator column therein, is formed in a first main surface of a semiconductor substrate whose crystal plane is a (110) plane. A crystal plane of a side surface of the trench in a short-side direction is a (111) plane, and a p-type diffusion layer constituting a p-column is formed in the above-mentioned side surface.

公开(公告)号：US20230023018A1

公开(公告)日：2023-01-26

申请号：US17380653

申请日：2021-07-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA

IPC: H01L25/065

Abstract: A semiconductor device includes a first semiconductor chip, an adhesive layer that is formed on the first semiconductor chip, and a second semiconductor chip that is arranged on the first semiconductor chip via the adhesive layer. The first semiconductor chip has a first semiconductor substrate and a first wiring layer. The first wiring layer has a first inductor and a first electrode pad. The first wiring layer is formed on the first semiconductor substrate. The second semiconductor chip has a second wiring layer and a second semiconductor substrate. The second wiring layer is formed on the first wiring layer via the adhesive layer. The second semiconductor substrate is formed on the second wiring layer, and has a first opening. In a plan view, the first electrode pad is formed so as not to overlap with the second semiconductor chip, and a second electrode pad overlaps with the first opening.

公开(公告)号：US20230022083A1

公开(公告)日：2023-01-26

申请号：US17380682

申请日：2021-07-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.

公开(公告)号：US20230016552A1

公开(公告)日：2023-01-19

申请号：US17946368

申请日：2022-09-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA

IPC: H01L23/485 ,  H01L29/872

Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.

公开(公告)号：US20220393027A1

公开(公告)日：2022-12-08

申请号：US17722778

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: In semiconductor device, a field plate portion having a high concentration p-type semiconductor region, a low concentration p-type semiconductor region having a lower impurity concentration than the high concentration p-type semiconductor region and a high concentration n-type semiconductor region is provided. Then, the high concentration p-type semiconductor region is electrically connected to the source region while the high concentration n-type semiconductor region is electrically connected to the drain region.

公开(公告)号：US20220013457A1

公开(公告)日：2022-01-13

申请号：US16924968

申请日：2020-07-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA ,  Shinichi UCHIDA

IPC: H01L23/522 ,  H01L49/02 ,  H03F3/04 ,  H03M1/12

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.

公开(公告)号：US20210343641A1

公开(公告)日：2021-11-04

申请号：US17190916

申请日：2021-03-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/495 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/74 ,  H01L49/02 ,  H01L21/56

Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.

公开(公告)号：US20200168545A1

公开(公告)日：2020-05-28

申请号：US16653127

申请日：2019-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Akio ONO ,  Shinichi KUWABARA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.

公开(公告)号：US20200161284A1

公开(公告)日：2020-05-21

申请号：US16598858

申请日：2019-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: H01L25/16 ,  H01L31/105 ,  H01L31/02 ,  H01L31/0232 ,  H01L23/373 ,  H01L23/00 ,  G02B6/42 ,  H04B10/40

Abstract: The semiconductor module includes a semiconductor chip and a semiconductor chip. The semiconductor chip includes an optical device such as an optical waveguide, an optical receiver, and a grating coupler, and a wiring formed over the optical device. The semiconductor chip includes a semiconductor element such as a MISFET formed in the semiconductor substrate, and a wiring formed over the semiconductor element. a top surface of the semiconductor chip is laminated to a top surface of the semiconductor chip such that the wirings are in direct contact with each other. In the semiconductor substrate, a through hole having a circular shape in plan view is formed, in the through hole, an insulating film is formed as a cladding layer, and the semiconductor substrate surrounded by the through hole constitutes an optical waveguide.