公开(公告)号：US08555119B2

公开(公告)日：2013-10-08

申请号：US13459932

申请日：2012-04-30

申请人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C8/16 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50012

摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.

摘要翻译： 用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。 测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。 表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。 表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。 在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。 表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。 选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

公开(公告)号：US08261138B2

公开(公告)日：2012-09-04

申请号：US11552158

申请日：2006-10-24

申请人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C8/16 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50012

摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.

摘要翻译： 用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。 测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。 表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。 表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。 在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。 表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。 选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

公开(公告)号：US08138820B2

公开(公告)日：2012-03-20

申请号：US13101139

申请日：2011-05-05

申请人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

发明人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

IPC分类号： H03K3/01

CPC分类号： H02M3/073 ,  H02M2003/077 ,  H03L5/00

摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

摘要翻译： 分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。 时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。 可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。 在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用 当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。

公开(公告)号：US20110204931A1

公开(公告)日：2011-08-25

申请号：US13101139

申请日：2011-05-05

申请人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

发明人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

IPC分类号： H03B19/00 ,  G05F3/02

CPC分类号： H02M3/073 ,  H02M2003/077 ,  H03L5/00

摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

摘要翻译： 分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。 时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。 可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。 在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用 当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。

公开(公告)号：US20110188295A1

公开(公告)日：2011-08-04

申请号：US12697956

申请日：2010-02-01

申请人： Fadi H. Gebara ,  Jente B. Kuang ,  Jayakumaran Sivagnaname ,  Ivan Vo

发明人： Fadi H. Gebara ,  Jente B. Kuang ,  Jayakumaran Sivagnaname ,  Ivan Vo

IPC分类号： G11C11/24 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/00 ,  G11C7/10 ,  G11C11/24

摘要： Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digital state. The digital charge propagates through the eDRAM sense amplifier circuitry to a mid-rail amplifier inverter circuit which amplifies the charge and provides it to a latch circuit. The latch circuit, in turn, inverts the charge to correctly represent at its output the logical value stored in the eDRAM cell being read, and returns the charge through the eDRAM sense amplifier circuitry to replenish the eDRAM cell.

摘要翻译： 嵌入式动态随机存取存储器（eDRAM）读出放大器电路，其中连接到第一多个eDRAM单元中的每一个的位线由与每个单元相连的单元控制线控制。 在读操作期间，eDRAM单元释放指示其数字状态的电荷。 数字电荷通过eDRAM读出放大器电路传播到放大电荷并将其提供给锁存电路的中间轨道放大器反相器电路。 锁存电路反过来反转电荷，以在其输出端正确地表示存储在正在读取的eDRAM单元中的逻辑值，并通过eDRAM读出放大器电路返回电荷以补充eDRAM单元。

公开(公告)号：US20100315132A1

公开(公告)日：2010-12-16

申请号：US12860302

申请日：2010-08-20

申请人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

发明人： Fadi H. Gebara ,  Jente B. Kuang ,  Abraham Mathews

IPC分类号： H03B19/00 ,  G05F1/10

CPC分类号： H02M3/073 ,  H02M2003/077 ,  H03L5/00

摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

摘要翻译： 分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。 时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。 可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。 在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用 当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。

公开(公告)号：US07760565B2

公开(公告)日：2010-07-20

申请号：US11781994

申请日：2007-07-24

申请人： Jente B. Kuang ,  Jerry C. Kao ,  Hung C. Ngo ,  Kevin J. Nowka ,  Liang-Teck Pang ,  Jayakumaran Sivagnaname

发明人： Jente B. Kuang ,  Jerry C. Kao ,  Hung C. Ngo ,  Kevin J. Nowka ,  Liang-Teck Pang ,  Jayakumaran Sivagnaname

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/50 ,  G01R31/31937 ,  G11C29/50012 ,  G11C2029/1202 ,  G11C2029/1204

摘要： A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.

摘要翻译： 用于评估存储单元访问时间的字线到位线定时环形振荡器电路提供关于内部位线访问定时的数据，特别是总字线选择到位线读出输出定时。 存储阵列的列以环形连接，形成环形振荡器。 每列的位线读取电路输出连接到下一列的字线选择输入，环绕环反转，从而形成环形振荡器。 环形振荡器的振荡周期由第一相的总字线选择到位线读取电路输出定时和另一相的预充电间隔时间决定，而位线读取时序主导。 该电路可以应用于小信号存储阵列，其中包括在环形振荡器周期内的读出放大器定时，或者包括读取评估电路时序的大信号存储阵列。

公开(公告)号：US07759980B2

公开(公告)日：2010-07-20

申请号：US11563888

申请日：2006-11-28

申请人： Jerry C. Kao ,  Jente B. Kuang ,  Alan J. Drake ,  Gary D. Carpenter ,  Fadi H. Gebara

发明人： Jerry C. Kao ,  Jente B. Kuang ,  Alan J. Drake ,  Gary D. Carpenter ,  Fadi H. Gebara

IPC分类号： H03K5/22

CPC分类号： H03K5/1534

摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.

摘要翻译： 在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及 状态捕捉块可操作地连接以接收当前信元信号。 将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号 检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

公开(公告)号：US07487374B2

公开(公告)日：2009-02-03

申请号：US11034556

申请日：2005-01-13

申请人： Ying Liu ,  Jente B. Kuang ,  Hung C. Ngo

发明人： Ying Liu ,  Jente B. Kuang ,  Hung C. Ngo

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171

摘要： Power-gated circuitry is put in a “sleep mode” that selectively gates both the power supply rails for static power control and the clock distribution for dynamic power control. A time interval M is established following a wake-up signal that includes the time to power-up, perform a computation, and return a result to the following circuitry. Likewise, a time interval N is established that indicates how long to wait after a result is returned before the power-gated circuitry is returned to the sleep mode to assure a desired performance. When a power-gated circuit is going to be needed for a future computation, it is issued a wake-up signal and a predetermined estimated time K for receipt of a next wake-up signal. A decision is made by analyzing the times M, N, and K as to when to return a power-gated circuit to the sleep mode following activation by a wake-up signal.

摘要翻译： 电源门控电路被置于“休眠模式”中，选择性地将电源轨两端门控，用于静态功率控制和用于动态功率控制的时钟分配。 在包括上电时间，执行计算并将结果返回到以下电路的唤醒信号之后建立时间间隔M. 类似地，建立时间间隔N，其指示在电源门控电路返回到睡眠模式之前在返回结果之后等待多久以确保期望的性能。 当将来需要一个电源门控电路时，它将发出一个唤醒信号和一个预定的估计时间K，用于接收下一个唤醒信号。 通过分析在唤醒信号激活之后何时将电源门控电路返回到休眠模式的时间M，N和K进行判断。

公开(公告)号：US07459950B2

公开(公告)日：2008-12-02

申请号：US11553014

申请日：2006-10-26

申请人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

发明人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

IPC分类号： H03K3/017

CPC分类号： H03K3/017 ,  G01R31/31727 ,  G06F1/10 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156

摘要： In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.

摘要翻译： 在本发明的示例性实施例中，在半导体中制造的本地时钟缓冲器（LCB）接收全局时钟信号作为输入。 LCB实现了可操作地耦合到LCB的脉冲宽度控制器和形成环形振荡器的输出驱动器。 输出驱动器输出脉宽调整信号。 脉冲宽度调整信号的脉冲宽度可通过脉冲宽度控制器进行调节，并与频率相关于全局时钟信号。 第二个环形振荡器（也称为nclk回路）也可以实现为服务器作为全局时钟信号。 脉冲宽度控制器可用于精确调整脉宽调整信号的脉宽。 可以实现脉冲宽度乘法器，以便直接观察和测量脉冲宽度调整信号的脉冲宽度。