中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

187 records (took 0.023 seconds)

    COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE-GENERATED REFERENCE SIGNALS
    51.
    发明申请
    COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE-GENERATED REFERENCE SIGNALS 有权

    公开(公告)号：US20210011867A1

    公开(公告)日：2021-01-14

    申请号：US16987472

    申请日：2020-08-07

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ian Shaeffer

    IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093

    Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

    Memory systems, modules, and methods for improved capacity
    52.
    发明授权
    Memory systems, modules, and methods for improved capacity 有权

    公开(公告)号：US10459660B2

    公开(公告)日：2019-10-29

    申请号：US15522164

    申请日：2015-11-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Scott C. Best

    IPC: G11C8/00 ,  G06F3/06 ,  G11C5/04 ,  G06F13/16

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

    Memory module register access
    54.
    发明授权
    Memory module register access 有权

    公开(公告)号：US10146608B2

    公开(公告)日：2018-12-04

    申请号：US15090399

    申请日：2016-04-04

    Applicant: Rambus Inc.

    Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

    IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

    Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Patent Agency Ranking