公开(公告)号：US07030675B1

公开(公告)日：2006-04-18

申请号：US10932642

申请日：2004-08-31

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

IPC分类号： H03H11/26

CPC分类号： H03K5/135 ,  H03K5/1252 ,  H03L7/0805 ,  H03L7/0814

摘要： A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

摘要翻译： 一种用于在DDR应用中更新由延迟链接收的控制信号的方法和装置。 寄存器用于调节到延迟链的控制信号。 当信号没有通过延迟链时，寄存器仅更新延迟链上的信号。 此外，本发明涉及一种延迟电路，其使用彼此并联连接的多个PMOS和NMOS晶体管以及提供所需延迟的反相器。 提供的延迟是通过顺序关闭/接通一系列NMOS / PMOS晶体管对来实现的。

公开(公告)号：US06946872B1

公开(公告)日：2005-09-20

申请号：US10623394

申请日：2003-07-18

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1774 ,  H03K19/17744

摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

公开(公告)号：US06825698B2

公开(公告)日：2004-11-30

申请号：US10229342

申请日：2002-08-26

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03B100

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US06667641B1

公开(公告)日：2003-12-23

申请号：US10056787

申请日：2002-01-23

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

IPC分类号： H03L708

CPC分类号： H03K19/1774 ,  H03K23/665 ,  H03K2005/00045 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/0997 ,  H03L7/183

摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

公开(公告)号：US06642758B1

公开(公告)日：2003-11-04

申请号：US09731473

申请日：2000-12-05

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

IPC分类号： H03L7095

CPC分类号： H03L7/0891 ,  H03F1/301 ,  H03H11/245 ,  H03K19/1774 ,  H03K23/665 ,  H03K2005/00045 ,  H03L7/081 ,  H03L7/089 ,  H03L7/0996 ,  H03L7/0997 ,  H03L7/18 ,  H03L7/183

摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

摘要翻译： 电路提供可编程相移特征，其中相移可由用户可编程地选择。 该电路可以并入可编程逻辑器件（PLD）或现场可编程门阵列（FPGA）中，以提供额外的可编程特性。 可编程相移电路可以在锁相环（PLL）或延迟锁定环（DLL）电路内实现。 在实现中，使用两个可编程计数器来实现可编程相移电路。

公开(公告)号：US06617884B2

公开(公告)日：2003-09-09

申请号：US10160355

申请日：2002-05-28

申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Khai Nguyen ,  Wayne Yeung ,  In Whan Kim

发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Khai Nguyen ,  Wayne Yeung ,  In Whan Kim

IPC分类号： H03D1300

CPC分类号： H03K19/1774 ,  H03K2005/00045 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/0997 ,  H03L7/183

摘要： A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

公开(公告)号：US06448820B1

公开(公告)日：2002-09-10

申请号：US09432442

申请日：1999-11-02

申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Khai Nguyen ,  Wayne Yeung ,  In Whan Kim

发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Khai Nguyen ,  Wayne Yeung ,  In Whan Kim

IPC分类号： H03D1300

CPC分类号： H03K19/1774 ,  H03K2005/00045 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/0997 ,  H03L7/183

摘要： A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

公开(公告)号：US06433579B1

公开(公告)日：2002-08-13

申请号：US09863143

申请日：2001-05-22

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Yan Chong ,  Philip Pan ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopinath Rangan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Yan Chong ,  Philip Pan ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopinath Rangan

IPC分类号： H03K19177

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

摘要： A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.

摘要翻译： 通过在设备上提供可根据可能使用的特定差分信令方案的需要进行配置的差分输出缓冲器，为各种差分信令方案配备了可编程逻辑器件。 缓冲器包括差分输出驱动器，电源电压和差分输出驱动器之间的可调节限流电路，以及差分输出驱动器和地之间的可调电流限制电路。 通过选择性地调节两个限流电路，可以控制输出阻抗和电流，以及共模输出电压和差分输出电压。

公开(公告)号：US06271729B1

公开(公告)日：2001-08-07

申请号：US09736065

申请日：2000-12-13

申请人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Robert R. N. Bielby

发明人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Robert R. N. Bielby

IPC分类号： H03L706

摘要： A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

公开(公告)号：US06177844B1

公开(公告)日：2001-01-23

申请号：US09393036

申请日：1999-09-09

申请人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Robert R. N. Bielby

发明人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Robert R. N. Bielby

IPC分类号： H03L706

CPC分类号： G06F1/10 ,  H03L7/0812 ,  H03L7/0996 ,  H03L7/0997

摘要： A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides aL substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）或延迟锁定环（“DLL”）电路，其中反馈回路电路在接收的设备上基本平行并复制时钟信号分配网络的一部分 主PLL / DLL输出信号。 以这种方式，分布式反馈回路电路更容易地提供对通过PLL / DLL电路服务的时钟信号分配网络传播的信号所经历的分布延迟的基本精确匹配。