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公开(公告)号：US07629813B2
公开(公告)日：2009-12-08
申请号：US11327530
申请日：2006-01-05
申请人： Robert Proebsting , Robert J. Drost , Ronald Ho
发明人： Robert Proebsting , Robert J. Drost , Ronald Ho
IPC分类号： H03K17/16
CPC分类号： H04L25/0272 , H04L25/0292
摘要： A system that dynamically refreshes the inputs of a differential receiver. During operation, while a differential transmitter is not transmitting data, the system applies substantially equal voltages to the outputs of the differential transmitter so that the differential voltage on the outputs of the differential transmitter is substantially zero. The system then refreshes the inputs of an associated differential receiver by applying substantially equal voltages to the inputs of the differential receiver so that the differential voltage on the inputs of the differential receiver is substantially zero. The differential transmitter is coupled to the differential receiver through a DC blocking mechanism, which prevents a DC voltage on the differential transmitter from reaching the differential receiver.
摘要翻译： 动态刷新差分接收器的输入的系统。 在操作期间，当差分发射机不发送数据时，系统对差分发射机的输出施加基本相等的电压，使得差分发射机的输出上的差分电压基本上为零。 然后，系统通过对差分接收器的输入施加基本上相等的电压来刷新相关联的差分接收器的输入，使得差分接收器的输入上的差分电压基本上为零。 差分发射器通过直流阻塞机构耦合到差动接收器，这阻止差分变送器上的直流电压到达差动接收器。
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公开(公告)号：US20090079498A1
公开(公告)日：2009-03-26
申请号：US11860693
申请日：2007-09-25
IPC分类号： H03G3/20
CPC分类号： H03F3/45973 , H03F1/30
摘要： A method for calibrating an offset voltage of an amplifier used to amplify capacitively coupled communication signals is described. During this process, a common voltage is applied to one or more inputs to the amplifier. Next, an output of the amplifier is iteratively, measured, and charge is applied to the one or more inputs until the offset voltage is less than a pre-determined value. Note that applying the charge may involve applying a sequence of one or more charge pulses.
摘要翻译： 描述了用于校准用于放大电容耦合通信信号的放大器的偏移电压的方法。 在该过程中，将公共电压施加到放大器的一个或多个输入。 接下来，迭代地，测量放大器的输出，并且将电荷施加到一个或多个输入，直到偏移电压小于预定值。 注意，应用电荷可以包括应用一个或多个充电脉冲的序列。
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53.发明授权公开(公告)号：US07395483B1
公开(公告)日：2008-07-01
申请号：US10966083
申请日：2004-10-15
申请人： Bernard Tourancheau , Ronald Ho , Robert J. Drost
发明人： Bernard Tourancheau , Ronald Ho , Robert J. Drost
IPC分类号： H03M13/37
CPC分类号： H03M13/09 , H03M13/098 , H03M13/2906
摘要： One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.
摘要翻译： 本发明的一个实施例提供一种便于检测和纠正错误的系统。 该系统通过在通信路径上接收由p个字组成的数据分组来进行操作，其中单词的每个比特在包含通信路径的一组数据线中的单独的数据线上被接收。 系统还在通信路径上接收时间签名t，其中t包含数据包中的p个字的每位错误信息。 当接收到数据包时，系统并行对数据包的每个数据位执行错误检测操作，其中错误检测操作针对数据包中的p个字的每个比特位置生成每位错误信息 。 最后，系统将生成的每位错误信息与时间签名t中相应的每位错误信息进行比较，以确定是否存在错误。
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54.发明授权Method and apparatus for electronically aligning capacitively coupled mini-bars 有权用于电容对齐电容耦合迷你条的方法和装置公开(公告)号：US07384804B2
公开(公告)日：2008-06-10
申请号：US11125792
申请日：2005-05-09
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , H01L23/48 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2224/0401
摘要： One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects a group of transmitter mini-bars on the first chip to form a transmitter bit position based on the measured alignment. In this way, the system allows a data signal to be distributed to and transmitted by the mini-bars that form the transmitter bit position. The system also selects a group of receiver mini-bars on the second chip to form a receiver bit position based on the measured alignment. Next, the system associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip based on the measured alignment. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.
摘要翻译： 本发明的一个实施例提供了一种系统，其电子地对准位于面对面的不同半导体芯片上的迷你条，以促进半导体芯片之间通过电容耦合的通信。 在操作期间，系统测量第一芯片和第二芯片之间的对准。 然后，系统在第一芯片上选择一组发射器迷你条，以基于测量的对准来形成发射机位置。 以这种方式，该系统允许将数据信号分配到形成发送器位位置的迷你条并发送。 该系统还在第二芯片上选择一组接收器迷你条，以形成基于测量对准的接收器位位置。 接下来，系统基于测量的对准将第一芯片上的发射机位位置与第二芯片上的接收器位置相关联。 以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。
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公开(公告)号：US07256628B2
公开(公告)日：2007-08-14
申请号：US10671641
申请日：2003-09-26
IPC分类号： H03L7/06
CPC分类号： G06F1/12
摘要： One embodiment of the present invention provides a system that matches speeds of asynchronous operation between a local chip and a neighboring chip. The system derives an internal frequency signal from an internal oscillator on the local chip, and receives an external frequency signal from a neighboring chip. The system then compares the internal frequency signal with the external frequency signal to generate a control signal, which is applied to the local chip to adjust the operating speed of the local chip, and applied to the internal oscillator to adjust the frequency of the internal oscillator.
摘要翻译： 本发明的一个实施例提供了一种匹配本地芯片和相邻芯片之间的异步操作速度的系统。 该系统从本地芯片上的内部振荡器得到内部频率信号，并从相邻芯片接收外部频率信号。 然后系统将内部频率信号与外部频率信号进行比较，以产生一个控制信号，该控制信号被施加到本地芯片上以调整本地芯片的工作速度，并施加到内部振荡器以调整内部振荡器的频率 。
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公开(公告)号：US07026867B2
公开(公告)日：2006-04-11
申请号：US10879606
申请日：2004-06-28
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： H03F1/02
CPC分类号： H03F3/45977 , H03F3/08
摘要： One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.
摘要翻译： 本发明的一个实施例提供一种具有不具有直流耦合的输入的电容耦合接收放大器。 在输入端编程一个直流电压。 在编程期间，发射机被保持在表示逻辑“1”的电压和表示逻辑“0”的电压之间的中点处的电压，并且接收机放大器的输入电压被编程为基本上是切换阈值 接收放大器的电压。 然后，在正常数据通信期间，发射机驱动耦合到接收放大器的高电平和低电信号。 由于接收机放大器的输入已基本设置为直流电压，所以接收放大器不需要控制电信号中每个转换的输入的直流电压。
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公开(公告)号：US06987412B2
公开(公告)日：2006-01-17
申请号：US10816761
申请日：2004-04-02
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/00013 , H01L2924/0002 , H03K3/037 , H03K17/689 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.
摘要翻译： 提出了一种用于锁存和放大电容耦合的芯片间通信信号的系统，其通过接收电容性接收器焊盘上的输入信号并通过反相器馈送输入信号以产生输出信号来操作。 输出信号通过弱化逆变器反馈，产生反馈信号，该反馈信号馈送到反相器的输入端，形成输入信号的锁存器。 弱化的逆变器被偏置以产生在高偏置电压V H H和低偏压V L之间摆动的反馈信号。 V H设定得比逆变器的切换阈值略高，并且将V L L设定得比切换阈值略低。 该反馈信号使得输入信号驻留在接近逆变器的开关阈值的窄电压范围内，从而使得反相器对输入信号中的小转变敏感。
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公开(公告)号：US06958538B1
公开(公告)日：2005-10-25
申请号：US10983250
申请日：2004-11-04
CPC分类号： G06F15/17375 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive coupling. This enables the multiple switch chips to communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms. The multiple switch chips in the proximity I/O switch are also configured to communicate with components in the computer system through conventional non-capacitive communication mechanisms.
摘要翻译： 本发明的一个实施例提供了一种接近I / O开关，其被配置为在计算机系统中的组件之间传送数据。 该接近I / O开关由多个开关芯片组成，它们通过电容耦合耦合在一起。 这使得多个开关芯片能够彼此通信，而不受传统的非电容通信机制的限制。 接近I / O开关中的多个开关芯片还被配置为通过传统的非电容通信机制与计算机系统中的组件进行通信。
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公开(公告)号：US06825708B1
公开(公告)日：2004-11-30
申请号：US10697914
申请日：2003-10-29
IPC分类号： G06G712
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H03F1/301 , H03F1/342 , H01L2924/00
摘要： An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.
摘要翻译： 一种用于消除偏移电压的感测电路的装置和方法。 具体地，在一个实施例中，CMOS反相放大器放大存在于输入节点处的输入信号。 电阻反馈电路耦合到CMOS反相放大器，用于消除与CMOS反相放大器相关联的偏移电压。 这通过将CMOS反相放大器偏置到其阈值电压来实现。 偏置电路耦合到电阻反馈电路，用于在亚阈值导通区域偏置电阻反馈电路中的MOSFET晶体管。 因此，电阻反馈电路对输入节点呈现高阻抗。 耦合到电阻反馈电路的钳位电路在亚阈值导通区域中保持电阻反馈电路中的晶体管的操作。
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公开(公告)号：US06696876B2
公开(公告)日：2004-02-24
申请号：US09759981
申请日：2001-01-12
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
IPC分类号： H03K300
摘要： A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.
摘要翻译： 一种用于设置和控制从多个输入时钟的内插导出的输出时钟的相位的时钟插值电路。 通过对多个时钟进行电容加权来执行插值。 选择和控制电路提供选择不同电容值以控制加权的能力。 还提供了可选的缓冲级，以锐化内插时钟的边沿转换。
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