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    Hybrid interconnect and system for testing semiconductor dice
    53.
    发明授权
    Hybrid interconnect and system for testing semiconductor dice 失效

    公开(公告)号：US07049840B1

    公开(公告)日：2006-05-23

    申请号：US09302576

    申请日：1999-04-30

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    IPC分类号： G01R31/02

    CPC分类号： G01R1/0466 ,  G01R1/0735

    摘要： An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.

    Test carrier with molded interconnect for testing semiconductor components
    57.
    发明授权
    Test carrier with molded interconnect for testing semiconductor components 失效
    带有模拟互连的测试载体，用于测试半导体元件

    公开(公告)号：US06353326B2

    公开(公告)日：2002-03-05

    申请号：US09143300

    申请日：1998-08-28

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    IPC分类号： G01R3102

    CPC分类号： G01R1/0483

    摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.

    摘要翻译： 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。

    Hybrid interconnect and system for testing semiconductor dice
    58.
    发明授权
    Hybrid interconnect and system for testing semiconductor dice 失效
    混合互连和半导体骰子测试系统

    公开(公告)号：US6025731A

    公开(公告)日：2000-02-15

    申请号：US821468

    申请日：1997-03-21

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    IPC分类号： G01R1/04 ,  G01R1/073 ,  G01R1/73

    CPC分类号： G01R1/0466 ,  G01R1/0735

    摘要： An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.

    摘要翻译： 提供用于与半导体管芯进行电连接的互连。 互连包括具有整体形成的接触构件的基板，其构造成电接触管芯上相应的接触位置。 互连还包括与衬底分开形成的导体图案，然后与接触构件电气连接到衬底。 导体可以安装到类似于TAB带的多层胶带上，或者可以直接粘合到基底上。 此外，每个导体可以包括与对应的接触构件对准的开口，并且填充有诸如导电粘合剂或焊料的导电材料。 导电材料电连接接触构件和导体，并且提供膨胀接头以允许导体的膨胀而不会压紧接触构件。 还提供了一种用于测试包括互连的骰子的系统，以及用于测试晶片的系统，其中互连形成为探针卡。

    Probe card for semiconductor wafers having mounting plate and socket
    59.
    发明授权
    Probe card for semiconductor wafers having mounting plate and socket 失效
    带安装板和插座的半导体晶圆探头卡

    公开(公告)号：US07250780B2

    公开(公告)日：2007-07-31

    申请号：US10742729

    申请日：2003-12-19

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    IPC分类号： G01R1/073 ,  G01R31/28

    CPC分类号： G01R31/2886

    摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

    摘要翻译： 提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。 探针卡被配置用于与测试电路电气通信的常规测试装置，例如晶片探测器处理器。 探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。 探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。 互连衬底可以由具有穿透突起的凸起接触构件的硅形成。 或者，接触构件可以形成为用于测试凸起的晶片的凹陷。 膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。 探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

    Method for fabricating a silicon carbide interconnect for semiconductor components
    60.
    发明授权
    Method for fabricating a silicon carbide interconnect for semiconductor components 失效
    制造半导体元件的碳化硅互连的方法

    公开(公告)号：US07033920B1

    公开(公告)日：2006-04-25

    申请号：US10187915

    申请日：2002-07-01

    申请人： Salman Akram ,  Alan G. Wood

    发明人： Salman Akram ,  Alan G. Wood

    IPC分类号： H01L21/44

    CPC分类号： H01L23/147 ,  G01R1/06711 ,  G01R1/06755 ,  G01R1/07314 ,  G01R3/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/49872 ,  H01L23/49877 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    摘要： An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the components. The interconnect contacts include silicon carbide conductive layers, and conductors in electrical communication with the silicon carbide conductive layers. The silicon carbide conductive layers provides a wear resistant surface, and improved heat transfer between the component contacts and the interconnect contacts. The silicon carbide conductive layers can comprise doped silicon carbide, or alternately thermally oxidized silicon carbide. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. In addition, the interconnect can be configured for constructing semiconductor packages and electronic assemblies such as multi chip modules.

    摘要翻译： 用于半导体部件的互连件包括衬底和衬底上的互连触点，用于电连接部件上的组件触点。 互连触点包括碳化硅导电层和与碳化硅导电层电连通的导体。 碳化硅导电层提供耐磨表面，并且改善部件触点和互连触点之间的热传递。 碳化硅导电层可以包括掺杂的碳化硅，或交替地热氧化的碳化硅。 互连可以被配置用于与用于测试分立元件（例如骰子或芯片尺寸封装）的测试设备一起使用，或者替代地与用于测试晶片尺寸的元件（例如晶片，面板和板）的测试设备一起使用。 此外，互连可以被配置用于构造半导体封装和诸如多芯片模块的电子组件。