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    Test carrier with molded interconnect for testing semiconductor components
    1.
    发明授权
    Test carrier with molded interconnect for testing semiconductor components 失效
    带有模拟互连的测试载体，用于测试半导体元件

    公开(公告)号：US06544461B1

    公开(公告)日：2003-04-08

    申请号：US09677555

    申请日：2000-10-02

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    IPC分类号： B29C4502

    CPC分类号： G01R1/0483

    摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.

    摘要翻译： 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。 可以在模制步骤期间使用垫圈来保护互连触点。

    Hybrid interconnect and system for testing semiconductor dice
    2.
    发明授权
    Hybrid interconnect and system for testing semiconductor dice 失效

    公开(公告)号：US07049840B1

    公开(公告)日：2006-05-23

    申请号：US09302576

    申请日：1999-04-30

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    IPC分类号： G01R31/02

    CPC分类号： G01R1/0466 ,  G01R1/0735

    摘要： An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.

    Test carrier with molded interconnect for testing semiconductor components
    4.
    发明授权
    Test carrier with molded interconnect for testing semiconductor components 失效
    带有模拟互连的测试载体，用于测试半导体元件

    公开(公告)号：US06353326B2

    公开(公告)日：2002-03-05

    申请号：US09143300

    申请日：1998-08-28

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    IPC分类号： G01R3102

    CPC分类号： G01R1/0483

    摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.

    摘要翻译： 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。

    Hybrid interconnect and system for testing semiconductor dice
    5.
    发明授权
    Hybrid interconnect and system for testing semiconductor dice 失效
    混合互连和半导体骰子测试系统

    公开(公告)号：US6025731A

    公开(公告)日：2000-02-15

    申请号：US821468

    申请日：1997-03-21

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    IPC分类号： G01R1/04 ,  G01R1/073 ,  G01R1/73

    CPC分类号： G01R1/0466 ,  G01R1/0735

    摘要： An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.

    摘要翻译： 提供用于与半导体管芯进行电连接的互连。 互连包括具有整体形成的接触构件的基板，其构造成电接触管芯上相应的接触位置。 互连还包括与衬底分开形成的导体图案，然后与接触构件电气连接到衬底。 导体可以安装到类似于TAB带的多层胶带上，或者可以直接粘合到基底上。 此外，每个导体可以包括与对应的接触构件对准的开口，并且填充有诸如导电粘合剂或焊料的导电材料。 导电材料电连接接触构件和导体，并且提供膨胀接头以允许导体的膨胀而不会压紧接触构件。 还提供了一种用于测试包括互连的骰子的系统，以及用于测试晶片的系统，其中互连形成为探针卡。

    Method for testing semiconductor components
    8.
    发明授权
    Method for testing semiconductor components 有权
    半导体元件测试方法

    公开(公告)号：US06208157B1

    公开(公告)日：2001-03-27

    申请号：US09298769

    申请日：1999-04-23

    申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

    发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

    IPC分类号： G01R3102

    CPC分类号： G01R1/0466 ,  G01R1/0433 ,  G01R1/0483

    摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.

    摘要翻译： 提供了一种用于测试半导体部件的系统和方法。 该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装在插座上用于容纳组件的载体。 载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。 此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。 插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。 在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。 然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

    Carrier and system for testing bumped semiconductor components
    9.
    发明授权
    Carrier and system for testing bumped semiconductor components 失效
    用于测试碰撞半导体元件的载体和系统

    公开(公告)号：US6040702A

    公开(公告)日：2000-03-21

    申请号：US888075

    申请日：1997-07-03

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

    IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R1/073 ,  G01R31/02 ,  H01L21/66 ,  H01L23/12 ,  H01L23/32 ,  H01R13/631 ,  H01R13/642 ,  H01R33/76

    CPC分类号： G01R1/0483 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/81385 ,  H01L2924/01021 ,  H01L2924/01087 ,  H01L2924/09701

    摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.

    摘要翻译： 提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。 载体包括基底，互连和力施加机构。 互连包括适于电接触接触凸块的接触构件的图案。 互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。 或者，互连可以是直接结合到载体的基底的多层带。 除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。 载体还可以包括配置成将部件与互连对准的对准部件。 该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

    Carrier and system for testing bumped semiconductor components
    10.
    发明授权
    Carrier and system for testing bumped semiconductor components 失效
    用于测试碰撞半导体元件的载体和系统

    公开(公告)号：US06313651B1

    公开(公告)日：2001-11-06

    申请号：US09322724

    申请日：1999-05-28

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

    IPC分类号： G01R3102

    CPC分类号： G01R1/0483 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2224/81385 ,  H01L2924/01021 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/00014

    摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.

    摘要翻译： 提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。 载体包括基底，互连和力施加机构。 互连包括适于电接触接触凸块的接触构件的图案。 互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。 或者，互连可以是直接结合到载体的基底的多层带。 除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。 载体还可以包括配置成将部件与互连对准的对准部件。 该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。