公开(公告)号：US20200013714A1

公开(公告)日：2020-01-09

申请号：US16168232

申请日：2018-10-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L27/11582 ,  H01L49/02

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

公开(公告)号：US20200013434A1

公开(公告)日：2020-01-09

申请号：US16168168

申请日：2018-10-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C5/06 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  G11C5/10 ,  G11C16/28 ,  G11C16/24 ,  G11C16/08

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the I/O pads.

公开(公告)号：US12125814B2

公开(公告)日：2024-10-22

申请号：US17667238

申请日：2022-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05007 ,  H01L2224/05073 ,  H01L2224/05565 ,  H01L2224/05573 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2224/0801 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/0913 ,  H01L2224/29187 ,  H01L2224/29188 ,  H01L2224/29575 ,  H01L2224/29687 ,  H01L2224/32145 ,  H01L2224/80895 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

公开(公告)号：US11778817B2

公开(公告)日：2023-10-03

申请号：US16912196

申请日：2020-06-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Kumar Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H10B43/27 ,  H01L21/762 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H10B41/27 ,  H01L21/02

CPC classification number: H10B43/27 ,  H01L21/76254 ,  H01L24/08 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02538 ,  H01L21/02595 ,  H01L21/02598 ,  H01L2224/08145

Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

公开(公告)号：US11728305B2

公开(公告)日：2023-08-15

申请号：US17317442

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Fumiaki Toyama ,  Peter Rabkin

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L49/02 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L28/60 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19104

Abstract: A semiconductor structure includes a bonded assembly of a first semiconductor die including first metal bonding pads and a second semiconductor die including second metal bonding pads, and a capacitor structure including a first electrode, a second electrode, and a node dielectric. The first electrode includes first bonded pairs of metal bonding pads. The second electrode includes second bonded pairs of metal bonding pads. The node dielectric includes portions dielectric material layers laterally surrounding the metal bonding pads.

公开(公告)号：US11646283B2

公开(公告)日：2023-05-09

申请号：US17357120

申请日：2021-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Masaaki Higashitani ,  Ramy Nashed Bassely Said

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/036 ,  H01L2224/05073 ,  H01L2224/05561 ,  H01L2224/08145 ,  H01L2224/80895

Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.

公开(公告)号：US11562975B2

公开(公告)日：2023-01-24

申请号：US17244387

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A bonded assembly of a first semiconductor die and a second semiconductor die includes first and second semiconductor dies. The first semiconductor die includes first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first metal bonding pads laterally surrounded by a semiconductor material layer. The second semiconductor die includes second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second metal bonding pads that include primary metal bonding pads and auxiliary metal bonding pads. The auxiliary metal bonding pads are bonded to the semiconductor material layer through metal-semiconductor compound portions formed by reaction of surface portions of the semiconductor material layer and an auxiliary metal bonding pad. The primary metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding.

公开(公告)号：US11538828B2

公开(公告)日：2022-12-27

申请号：US16984920

申请日：2020-08-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H01L29/417 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556

Abstract: A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.

公开(公告)号：US11508748B2

公开(公告)日：2022-11-22

申请号：US16887818

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Peter Rabkin ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L23/522 ,  H01L27/11543 ,  H01L27/11556 ,  H01L29/207 ,  H01L27/11524

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US11424215B2

公开(公告)日：2022-08-23

申请号：US17094543

申请日：2020-11-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L23/00 ,  H01L25/00 ,  H01L27/11582 ,  H01L21/50 ,  H01L23/532 ,  H01L27/11556 ,  H01L21/60

Abstract: A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.