公开(公告)号：US20180107568A1

公开(公告)日：2018-04-19

申请号：US15785577

申请日：2017-10-17

Applicant: Seagate Technology LLC

Inventor： Jay Allen Sheldon ,  Ryan James Goss

IPC: G06F11/16 ,  G06F3/06

CPC classification number: G11C7/04 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/0727 ,  G06F11/0751

Abstract: An unrecoverable error is determined when attempting to access data stored in a target memory unit of a storage medium of a data storage device. Access to neighboring memory units that are proximate to the target memory unit is controlled in response. The controlling of the access affects a temperature of the target memory unit over a period of time. After the period of time, access to the data is attempted from the target memory unit.

公开(公告)号：US09946462B1

公开(公告)日：2018-04-17

申请号：US15044007

申请日：2016-02-15

Applicant: Seagate Technology LLC

Inventor： Peng Li ,  Kevin Arthur Gomez ,  Ryan James Goss

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/109

CPC classification number: G06F3/0608 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/1009 ,  G06F12/109 ,  G06F2212/65

Abstract: Mapping table entries that map logical block addresses to physical block addresses can be intercepted and compressed to save space. In some cases, the mapping table entries can be compressed into compression units, which can hold multiple mapping table entries. Portions of the mapping table entries can be arranged into groups, and a group can be compressed with a unique compression method. The compression method used to compress a group may be based on data characteristics of the group. When data corresponding to the mapping table entries are read or modified, the compressed data can be decompressed and provided to a requesting controller or processor. When the mapping table entry is modified, the updated mapping entry may be arranged into groups, and the groups can be compressed and stored to the compression units.

公开(公告)号：US09823841B2

公开(公告)日：2017-11-21

申请号：US14486201

申请日：2014-09-15

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Ryan James Goss ,  Jeffrey L. Whaley ,  Dana Simonson

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F3/06 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0661 ,  G06F3/0679

Abstract: A definition is received of at least one data object and a compute object from a host at a storage compute device. A first key is associated with the at least one data object and a second key is associated with the compute object. A command is received from the host to perform a computation that links the first and second keys. The computation is defined by the compute object and acts on the data object. The computation is performed via the storage compute device using the compute object and the data object in response to the command.

公开(公告)号：US09727459B2

公开(公告)日：2017-08-08

申请号：US14466143

申请日：2014-08-22

Applicant: Seagate Technology LLC

Inventor： Antoine Khoueir ,  Ryan James Goss ,  Jon Trantham ,  Kevin Gomez ,  Frank Dropps

IPC: G06F12/06 ,  G11C7/00 ,  G06F3/06 ,  G06F12/00 ,  G11C7/10 ,  G11C16/04 ,  G11C16/26 ,  G11C15/04

CPC classification number: G06F12/06 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0638 ,  G06F2206/1014 ,  G11C7/00 ,  G11C7/1006 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5641

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

公开(公告)号：US20160085291A1

公开(公告)日：2016-03-24

申请号：US14495215

申请日：2014-09-24

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Ryan James Goss ,  Jeffrey L. Whaley ,  Dana Simonson

IPC: G06F1/32

CPC classification number: G06F1/3268 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296

Abstract: Computations are performed on data objects via two or more data storage sections. The data storage sections facilitate persistently storing the data objects in parallel read/write operations. The data objects are used in computations within a storage compute device. At least one of the storage sections is deactivated during the computations to reduce power usage of the storage compute device.

Abstract translation: 通过两个或多个数据存储部分对数据对象执行计算。 数据存储部分便于将数据对象持续存储在并行读/写操作中。 数据对象用于存储计算设备内的计算。 在计算期间，至少一个存储部分被去激活以减少存储计算设备的功率使用。

公开(公告)号：US09201728B2

公开(公告)日：2015-12-01

申请号：US14025327

申请日：2013-09-12

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Ryan James Goss ,  Mark Allen Gaertner ,  Bruce Douglas Buch ,  Arvind Sridharan

IPC: G06F11/10

CPC classification number: G06F11/1012

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，该装置具有固态非易失性存储器和被配置为将数据写入存储器的选定位置的处理电路。 数据以多位码字的形式排列，每个码字包括用户数据有效载荷和被配置为校正用户数据有效载荷中的一个或多个位错误的相关联的奇偶校验数据。 所述处理电路至少根据所选择的位置的访问操作的累积计数中的至少一个来选择所述码字的大小，所述用户数据有效载荷的大小或所述奇偶校验数据的大小中的一个， 与所选位置相关联的错误率。

公开(公告)号：US09164832B2

公开(公告)日：2015-10-20

申请号：US13779434

申请日：2013-02-27

Applicant: Seagate Technology LLC

Inventor： Mark Allen Gaertner ,  Ryan James Goss ,  Antoine Khoueir ,  Ara Patapoutian

IPC: G11C29/00 ,  G06F11/10 ,  G11C17/16 ,  G11C13/00

CPC classification number: G06F11/1048 ,  G06F11/1008 ,  G06F11/1044 ,  G11C13/0002 ,  G11C17/165

Abstract: A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.

Abstract translation: 一般来说，数据存储设备可被构造和操作至少一个控制器，该控制器被配置为在至少一个可变电阻存储器单元中识别来自预定阈值的方差，并将第一纠错码（ECC）级别升级到第二ECC级别 至少一个可变电阻存储单元。

公开(公告)号：US20150187413A1

公开(公告)日：2015-07-02

申请号：US14595757

申请日：2015-01-13

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Ryan James Goss ,  Antoine Khoueir

IPC: G11C13/00 ,  G11C11/56 ,  G11C29/08

CPC classification number: G11C13/0002 ,  G11C7/04 ,  G11C11/56 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/08 ,  G11C2013/0076

Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.

Abstract translation: 测量影响基于电阻的非易失性存储器的存储单元的两个或多个工作负载指示器。 两个或多个工作负载指示符被应用于响应于两个或更多个工作负载指示器预测电阻偏移和/或电阻噪声方差的传递函数。 应用传递函数的结果来移位和/或确定用于影响存储器单元的程序操作和读取操作中的至少一个的阈值电阻。 结果，存储单元的错误率降低。

公开(公告)号：US09058869B2

公开(公告)日：2015-06-16

申请号：US13761301

申请日：2013-02-07

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Antoine Khoueir ,  Ryan James Goss ,  Jon D. Trantham

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C11/5614 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0033

Abstract: Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.

Abstract translation: 数据被写入基于电阻的非易失性存储器的单元。 自从将数据写入单元格后，会跟踪活动度量。 响应于满足阈值的活动度量，将偏置信号施加到单元以反转单元的电阻偏移。

公开(公告)号：US20150089119A1

公开(公告)日：2015-03-26

申请号：US14034211

申请日：2013-09-23

Applicant: Seagate Technology LLC

Inventor： Kris Conklin ,  Bruce Dunlop ,  Mark Allen Gaertner ,  Ryan James Goss

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F13/161 ,  G06F2212/1016 ,  G06F2212/7203

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command.

Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，存储器模块具有多个固态非易失性存储单元。 控制器传达具有地址信息的第一命令和第一操作码。 第一操作代码识别存储器模块相对于地址信息采取的第一动作。 控制器随后传送具有第二操作码的第二命令，而没有相应的地址信息。 存储器模块使用来自第一命令的地址信息采用由第二命令标识的第二动作。