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    Phase frequency detectors generating minimum pulse widths
    51.
    发明授权
    Phase frequency detectors generating minimum pulse widths 有权
    产生最小脉冲宽度的相位频率检测器

    公开(公告)号：US07633349B2

    公开(公告)日：2009-12-15

    申请号：US11696575

    申请日：2007-04-04

    申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

    发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

    IPC分类号： H03L1/00

    CPC分类号： H03D13/004

    摘要： A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

    摘要翻译： 相位频率检测器将参考时钟信号与反馈时钟信号进行比较，以在一个或多个输出信号中产生脉冲。 一个或多个输出信号具有最小的脉冲宽度。 相位频率检测器具有温度检测电路。 相位频率检测器使用温度检测电路调节一个或多个输出信号的最小脉冲宽度，以补偿相位频率检测器的温度变化。

    Wide range and dynamically reconfigurable clock data recovery architecture
    52.
    发明申请
    Wide range and dynamically reconfigurable clock data recovery architecture 有权
    宽范围和动态可重构的时钟数据恢复架构

    公开(公告)号：US20090122939A1

    公开(公告)日：2009-05-14

    申请号：US11329197

    申请日：2006-01-09

    申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong ,  Rakesh H. Patel

    发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong ,  Rakesh H. Patel

    IPC分类号： H04L7/00

    CPC分类号： H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

    摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.

    摘要翻译： 宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 可以在不关闭电路或PLD的情况下动态重新编程参数。 这允许CDR电路在各种标准和协议之间进行即时切换。

    Techniques for reconfiguring programmable circuit blocks
    53.
    发明授权
    Techniques for reconfiguring programmable circuit blocks 有权
    重新配置可编程电路块的技术

    公开(公告)号：US07532029B1

    公开(公告)日：2009-05-12

    申请号：US11737079

    申请日：2007-04-18

    申请人： Kazi Asaduzzaman ,  Leon Zheng ,  Sergey Shumarayev ,  Tim Tri Hoang

    发明人： Kazi Asaduzzaman ,  Leon Zheng ,  Sergey Shumarayev ,  Tim Tri Hoang

    IPC分类号： H03K19/173 ,  H03L7/00

    CPC分类号： H03K19/1733 ,  H03K19/17752 ,  H03L7/081 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/0996 ,  H03L7/18

    摘要： Techniques are provided for dynamically reconfiguring programmable circuit blocks on integrated circuits during user mode. First configuration bits are loaded from first configuration scan registers into second configuration scan registers during configuration mode. The first configuration bits are used to configure programmable settings of a programmable circuit block. During user mode, second configuration bits are transmitted from a pin to the second configuration scan registers without transferring the second configuration bits through the first configuration scan registers. The second configuration bits are used to reconfigure the programmable settings of the programmable circuit block during the user mode. Also, phase shift circuitry can dynamically shift the phase of an output clock signal by selecting a different input clock signal. The phase shift circuitry has a delay circuit that allows the phase of a high frequency clock signal to be shifted without causing glitches in the clock signal.

    摘要翻译： 提供技术用于在用户模式期间动态地重新配置集成电路上的可编程电路块。 在配置模式下，第一个配置位从第一个配置扫描寄存器加载到第二个配置扫描寄存器中。 第一个配置位用于配置可编程电路块的可编程设置。 在用户模式期间，第二配置位从引脚传输到第二配置扫描寄存器，而不通过第一配置扫描寄存器传输第二配置位。 第二个配置位用于在用户模式期间重新配置可编程电路块的可编程设置。 此外，相移电路可以通过选择不同的输入时钟信号来动态地移位输出时钟信号的相位。 相移电路具有允许高频时钟信号的相位被移位而不引起时钟信号的毛刺的延迟电路。

    Digital adaptation circuitry and methods for programmable logic devices
    56.
    发明申请
    Digital adaptation circuitry and methods for programmable logic devices 有权
    用于可编程逻辑器件的数字适配电路和方法

    公开(公告)号：US20080069276A1

    公开(公告)日：2008-03-20

    申请号：US11522284

    申请日：2006-09-14

    申请人： Wilson Wong ,  Doris Po Ching Chan ,  Simardeep Maangat ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    发明人： Wilson Wong ,  Doris Po Ching Chan ,  Simardeep Maangat ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

    IPC分类号： H04B1/10

    CPC分类号： H04L25/03885

    摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

    摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

    Decision feedback equalization for variable input amplitude
    57.
    发明授权
    Decision feedback equalization for variable input amplitude 有权
    用于可变输入幅度的判决反馈均衡

    公开(公告)号：US08416845B1

    公开(公告)日：2013-04-09

    申请号：US11484285

    申请日：2006-07-11

    申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

    发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H04L25/03057 ,  H03K5/1532

    摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.

    摘要翻译： 提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。 方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。 均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。 抽头系数可以由均衡电路自动调整。

    Half-rate DFE with duplicate path for high data-rate operation
    58.
    发明授权
    Half-rate DFE with duplicate path for high data-rate operation 有权
    具有高数据速率操作的重复路径的半速率DFE

    公开(公告)号：US07782935B1

    公开(公告)日：2010-08-24

    申请号：US11514490

    申请日：2006-08-31

    申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

    发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

    IPC分类号： H03H7/30

    CPC分类号： H03H11/26 ,  H04L25/03878 ,  H04L2025/0349

    摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.

    摘要翻译： 提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。 半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。 可以使用以输入信号数据速率的一半工作的两个延迟链电路。 更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。 多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。 重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。 第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

    Modular buffering circuitry for multi-channel transceiver clock and other signals
    59.
    发明授权
    Modular buffering circuitry for multi-channel transceiver clock and other signals 有权
    用于多通道收发器时钟和其他信号的模块化缓冲电路

    公开(公告)号：US07304507B1

    公开(公告)日：2007-12-04

    申请号：US11288496

    申请日：2005-11-28

    申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

    发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

    IPC分类号： H03K19/00

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： Circuitry for distributing signals such as reference clock signals among blocks of transceiver circuitry on an integrated circuit such as a field programmable gate array (“FPGA”) employs bidirectional buffers rather than unidirectional buffers. This allows all buffers to have the same construction regardless of physical location, which facilitates construction of the circuitry using identical or substantially identical modules. The same approach may be used for distributing other types of signals among the transceiver blocks. For example, this approach may be used for distributing calibration control signals.

    摘要翻译： 在集成电路（例如现场可编程门阵列（“FPGA”）上的收发器电路块之间分配诸如参考时钟信号的信号的电路采用双向缓冲器而不是单向缓冲器。 这允许所有缓冲器具有相同的结构，而不管物理位置如何，这有助于使用相同或基本相同的模块构建电路。 相同的方法可以用于在收发器块之间分配其他类型的信号。 例如，该方法可用于分配校准控制信号。