公开(公告)号：US20150180475A1

公开(公告)日：2015-06-25

申请号：US14409310

申请日：2012-07-06

申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： H03K19/0175

CPC分类号： H03K19/017509 ,  H03K19/00384 ,  H03K19/018521

摘要： An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. The at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period. The at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period.

摘要翻译： 描述了一个输入/输出（IO）驱动电路。 IO缓冲器驱动器电路包括：用于接收输入信号的至少一个输入和用于提供至少一个输出信号的至少一个输出; 以及多个开关，被布置成向所述至少一个输出端提供低电压值和高电压值之间的可变电压电平。 多个开关中的至少一个第一开关被布置成在第一时间段内启动电压变化到低电压值和高电压值之间的中间电压电平。 多个开关中的至少一个第二开关被布置成在第二时间段内将电压变化继续到低电压值或高电压值。

公开(公告)号：US08836414B2

公开(公告)日：2014-09-16

申请号：US12093939

申请日：2005-11-15

申请人： Yehim-Haim Fefer ,  Sergey Sofer

发明人： Yehim-Haim Fefer ,  Sergey Sofer

IPC分类号： G05F1/10 ,  G05F1/46

CPC分类号： G05F1/465 ,  G05F1/565

摘要： A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. A method for compensating for voltage drops in an integrated circuit, the method includes providing at least a first supply voltage to an integrated circuit; the method is characterized by including: comparing between a voltage level at a sensing point within an integrated circuit to a reference voltage derived from a voltage peak level at the sensing point; and selectively increasing the voltage at the sensing point in response to the comparison.

摘要翻译： 一种包括至少一个电流消耗部件的装置。 该装置的特征在于包括补偿电路，其适于在集成电路内的感测点处的电压电平与从感测点处的电压峰值电平导出的参考电压之间进行比较; 并且响应于比较选择性地增加感测点处的电压。 一种用于补偿集成电路中的电压降的方法，所述方法包括至少向集成电路提供第一电源电压; 该方法的特征在于包括：将集成电路内的感测点处的电压电平与从感测点处的电压峰值电平导出的参考电压进行比较; 并且响应于该比较选择性地增加感测点处的电压。

公开(公告)号：US08384437B2

公开(公告)日：2013-02-26

申请号：US13062961

申请日：2008-09-15

申请人： Sergey Sofer ,  Ami Dabush ,  Michael Priel

发明人： Sergey Sofer ,  Ami Dabush ,  Michael Priel

IPC分类号： H03K19/00

CPC分类号： H03K19/096 ,  G06F1/08 ,  H03K19/0016

摘要： A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic. The polarity comparison logic and the selector logic being further arranged such that, upon the enable signal transitioning from an active state to an inactive state, the selected clock signal provided to the clock freezing logic comprises a polarity substantially equivalent to that of the gated clock signal.

摘要翻译： 一种包括时钟门控逻辑的半导体器件。 时钟门控逻辑包括布置成接收所选择的时钟信号和使能信号的时钟冻结逻辑。 时钟冻结逻辑还被布置成当使能信号包括非活动状态时，输出基本上对应于所选择的时钟信号的选通时钟信号，并且当使能信号包括有效状态时，冻结输出门控时钟信号。 时钟门控逻辑还包括极性比较逻辑，其被布置为比较输入时钟信号和门控时钟信号的极性以及布置成从输入时钟信号和反相输入时钟信号中选择逻辑的选择器逻辑， 输入时钟信号的极性和门控时钟信号，并将所选择的时钟信号提供给时钟冻结逻辑。 极性比较逻辑和选择器逻辑被进一步布置成使得在使能信号从有效状态转换到非活动状态时，提供给时钟冻结逻辑的所选择的时钟信号包括基本上等于门控时钟信号的极性的极性 。

公开(公告)号：US20130027082A1

公开(公告)日：2013-01-31

申请号：US13635166

申请日：2010-04-22

申请人： Sergey Sofer ,  Michael Priel ,  Dov Tyztkin

发明人： Sergey Sofer ,  Michael Priel ,  Dov Tyztkin

IPC分类号： H03K19/0185

CPC分类号： H03K3/356113

摘要： A voltage level shifter for translating a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The voltage level shifter comprises an input port for receiving the binary input signal as an input voltage varying between a first input voltage level and a second input voltage level. An output port is connected to a node for outputting the binary output signal as an output voltage varying between a first output voltage level and a second output voltage level. A supply voltage node connectable to a voltage supply, can provide the second output voltage level. A first switch is arranged to couple the supply voltage node to the node and to decouple the supply voltage node from the node based on a voltage at the node. A feedback voltage loop is connected to the node for providing a feedback voltage based on the voltage at the node. A second switch is connected to the feedback voltage loop and arranged to couple the input port to the node based on a voltage at the input port and the feedback voltage. A decoupler and a voltage shifting method are also disclosed.

摘要翻译： 电压电平移位器，用于将表示二进制序列的二进制输入信号转换成表示相同二进制序列的二进制输出信号。 电压电平移位器包括用于接收二进制输入信号作为在第一输入电压电平和第二输入电压电平之间变化的输入电压的输入端口。 输出端口连接到节点，用于输出二进制输出信号作为在第一输出电压电平和第二输出电压电平之间变化的输出电压。 可连接到电源的电源电压节点可以提供第二输出电压电平。 第一开关被布置成将电源电压节点耦合到节点，并且基于节点处的电压将电源电压节点与节点去耦。 反馈电压回路连接到节点，用于基于节点处的电压提供反馈电压。 第二开关连接到反馈电压回路，并且被布置成基于输入端口处的电压和反馈电压将输入端口耦合到节点。 还公开了解耦器和电压移位方法。

公开(公告)号：US20120038367A1

公开(公告)日：2012-02-16

申请号：US13255523

申请日：2009-03-31

申请人： Yefim-Haim Fefer ,  Sergey Sofer ,  Boris Zapesochini

发明人： Yefim-Haim Fefer ,  Sergey Sofer ,  Boris Zapesochini

IPC分类号： G01R31/04

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  G01R31/31717

摘要： An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal.

摘要翻译： 一种集成电路器件，包括包含在封装中的半导体管芯。 集成电路装置包括一个或多个内部连接验证模块，用于响应于相应的内部电源节点处的电压与参考电压之间的电压差来确定测试装置的不良连接信号，该电压差表示 电源连接到包装上的电源端子之一。 测试装置可以包括用于响应于指示存在或不存在伴随着不良连接信号的不断的缺陷的逻辑信号而拒绝或接受集成电路装置的指示符或分类元件，并且用于处理集成电路 响应于不良连接信号的断言而独立地设备。

公开(公告)号：US08089259B2

公开(公告)日：2012-01-03

申请号：US12261599

申请日：2008-10-30

申请人： Sergey Sofer ,  Vlad Goldman ,  Dov Tzytkin

发明人： Sergey Sofer ,  Vlad Goldman ,  Dov Tzytkin

IPC分类号： G05F3/16 ,  G05F3/20

CPC分类号： H02J1/14 ,  H03K19/0016 ,  H03K19/00361

摘要： A system that has low power recovery capabilities, the system includes: a switch that is adapted to provide a gated power supply to a power gated circuit in response to a control current; and a control signal generator adapted to control an intensity of the control current in response to a reception of a low power period end indicator, a value of the continuous supply voltage at a port of the control signal generator, a value of the gated supply voltage and an output signal of a high switching point buffer that is inputted by the gated supply voltage.

摘要翻译： 一种具有低功率恢复能力的系统，该系统包括：开关，适于响应于控制电流向门电路提供门控电源; 以及控制信号发生器，其适于响应于低功率周期结束指示符的接收来控制控制电流的强度，控制信号发生器端口处的连续电源电压的值，门控电源电压的值 以及由门控电源电压输入的高切换点缓冲器的输出信号。

公开(公告)号：US20110156752A1

公开(公告)日：2011-06-30

申请号：US13062961

申请日：2008-09-15

申请人： Sergey Sofer ,  Ami Dabush ,  Michael Priel

发明人： Sergey Sofer ,  Ami Dabush ,  Michael Priel

IPC分类号： H03K19/21 ,  H03K19/00

CPC分类号： H03K19/096 ,  G06F1/08 ,  H03K19/0016

摘要： A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic. The polarity comparison logic and the selector logic being further arranged such that, upon the enable signal transitioning from an active state to an inactive state, the selected clock signal provided to the clock freezing logic comprises a polarity substantially equivalent to that of the gated clock signal.

摘要翻译： 一种包括时钟门控逻辑的半导体器件。 时钟门控逻辑包括布置成接收所选择的时钟信号和使能信号的时钟冻结逻辑。 时钟冻结逻辑还被布置成当使能信号包括非活动状态时，输出基本上对应于所选择的时钟信号的选通时钟信号，并且当使能信号包括有效状态时，冻结输出门控时钟信号。 时钟门控逻辑还包括极性比较逻辑，其被布置为比较输入时钟信号和门控时钟信号的极性以及布置成从输入时钟信号和反相输入时钟信号中选择逻辑的选择器逻辑， 输入时钟信号的极性和门控时钟信号，并将所选择的时钟信号提供给时钟冻结逻辑。 极性比较逻辑和选择器逻辑被进一步布置成使得在使能信号从有效状态转换到非活动状态时，提供给时钟冻结逻辑的所选择的时钟信号包括基本上等于门控时钟信号的极性的极性 。

公开(公告)号：US09503088B2

公开(公告)日：2016-11-22

申请号：US14655150

申请日：2013-01-10

申请人： Sergey Sofer ,  Michael Priel ,  Noam Sivan

发明人： Sergey Sofer ,  Michael Priel ,  Noam Sivan

IPC分类号： H03K19/003 ,  H03K19/0944

CPC分类号： H03K19/00384 ,  H03K19/0944

摘要： The invention provides a method for recovering NBTI/PBTI related parameter degradation in MOSFET devices. The method includes operating the at least one MOSFET device in a standby mode, exiting the at least one MOSFET device from the standby mode, holding the at least one MOSFET device in an active state for a predetermined time span after exiting the standby mode, and operating the at least one MOSFET device in an operational mode after the predetermined time span has elapsed.

摘要翻译： 本发明提供一种用于恢复MOSFET器件中的NBTI / PBTI相关参数劣化的方法。 该方法包括在备用模式下操作至少一个MOSFET器件，将至少一个MOSFET器件从备用模式退出，在退出待机模式之后将至少一个MOSFET器件保持在预定时间间隔内的活动状态;以及 在经过预定时间间隔之后，在操作模式下操作至少一个MOSFET器件。

公开(公告)号：US09368162B2

公开(公告)日：2016-06-14

申请号：US13983145

申请日：2011-02-08

申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： G11C5/14 ,  G06F1/32

CPC分类号： G11C5/14 ,  G06F1/3225 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D50/20

摘要： An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at least one memory sub-module is redundant, and place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant.

摘要翻译： 一种集成电路装置，包括至少一个包括多个存储器子模块的存储器模块，以及至少一个功率管理模块，被布置成为所述至少一个存储器模块提供功率管理。 所述至少一个电源管理模块被布置成确定至少一个存储器子模块的内容何时是冗余的，并且在确定所述至少一个存储器的内容之后将所述至少一个存储器子模块置于掉电状态 子模块是多余的。

公开(公告)号：US09354645B2

公开(公告)日：2016-05-31

申请号：US14115223

申请日：2011-05-27

申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： G05F1/56 ,  G05F1/46 ,  G05F1/563 ,  H02M1/00

CPC分类号： G05F1/468 ,  G05F1/465 ,  G05F1/56 ,  G05F1/563 ,  H02M2001/0025 ,  Y10T307/406

摘要： A voltage regulating circuit is provided for regulating an output voltage in order to minimize an absolute difference between a level of said output voltage and a reference level. The voltage regulating circuit comprises a voltage regulator and a reference level generator. The reference level generator generates an internal reference level on the basis of said output voltage level and said reference level such that said internal reference level does not exceed said output voltage level by more than a maximum allowed increment. The voltage regulator regulates said output voltage in order to minimize an absolute difference between said output voltage level and said internal reference level. A method of regulating an output voltage is also disclosed.

摘要翻译： 提供电压调节电路，用于调节输出电压，以使所述输出电压的电平和参考电平之间的绝对差最小化。 电压调节电路包括电压调节器和参考电平发生器。 参考电平发生器基于所述输出电压电平和所述参考电平产生内部参考电平，使得所述内部参考电平不超过所述输出电压电平超过允许的最大增量。 电压调节器调节所述输出电压，以便最小化所述输出电压电平和所述内部参考电平之间的绝对差。 还公开了一种调节输出电压的方法。