公开(公告)号：US07847335B2

公开(公告)日：2010-12-07

申请号：US11402529

申请日：2006-04-11

申请人： Tzyh-Cheang Lee ,  Tsung-Lin Lee ,  Jiunn-Ren Hwang

发明人： Tzyh-Cheang Lee ,  Tsung-Lin Lee ,  Jiunn-Ren Hwang

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile semiconductor memory device includes a gate stack formed on a substrate, semiconductor spacers, an oxide-nitride-oxide stack, and a contact pad. The semiconductor spacers are adjacent to sides of the gate stack and over the substrate. The oxide-nitride-oxide stack is located between the spacers and the gate stack, and located between the spacers and the substrate, such that the oxide-nitride-oxide stack has a generally L-shaped cross-section on at least one side of the gate stack. The contact pad is over and in electrical contact with the gate electrode and the semiconductor spacers. The contact pad may be further formed into recessed portions of the oxide-nitride-oxide stack between the gate electrode and the semiconductor spacers. The contact pad may include an epitaxial silicon having a metal silicide formed thereon.

摘要翻译： 非易失性半导体存储器件包括形成在衬底，半导体间隔物，氧化物 - 氮化物 - 氧化物堆叠和接触焊盘上的栅堆叠。 半导体间隔物邻近栅极堆叠的两侧并在衬底上方。 氧化物 - 氧化物 - 氧化物堆叠位于间隔物和栅极堆叠之间，并且位于间隔物和衬底之间，使得氧化物 - 氧化物 - 氧化物堆叠在至少一侧上具有大致L形的横截面 门堆叠。 接触垫在栅极电极和半导体间隔物之间​​是电接触的。 接触焊盘可以进一步形成在栅电极和半导体间隔物之间​​的氧化物 - 氮化物 - 氧化物堆叠的凹陷部分。 接触焊盘可以包括其上形成有金属硅化物的外延硅。

公开(公告)号：US20070161195A1

公开(公告)日：2007-07-12

申请号：US11327185

申请日：2006-01-06

申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923 ,  Y10S438/954

摘要： A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.

摘要翻译： 提供了一种用于侧壁SONOS存储器件的系统和方法。 电子设备包括非易失性存储器。 衬底包括源极/漏极区域。 栅极堆叠直接在衬底上并且在源极/漏极区域之间。 栅极堆叠具有侧壁。 在栅叠层附近形成氮化物间隔物。 第一氧化物材料直接邻近间隔物形成。 在间隔物和栅极叠层之间形成氧化物 - 氧化物 - 氧化物结构。 氧化物 - 氧化物 - 氧化物结构在栅极堆叠的至少一侧具有大致L形的横截面。 氧化物 - 氮化物 - 氧化物结构包括垂直部分和水平部分。 垂直部分基本上与侧壁对准并且位于第一氧化物材料和栅极侧壁之间。 水平部分基本上与衬底对准并位于第一氧化物和衬底之间。

公开(公告)号：US20050002472A1

公开(公告)日：2005-01-06

申请号：US10609496

申请日：2003-07-01

申请人： Tsung-Lin Lee ,  Rong-Liang Chiou

发明人： Tsung-Lin Lee ,  Rong-Liang Chiou

IPC分类号： H04L25/06 ,  H04L27/26 ,  H04L27/38 ,  H04L27/06

CPC分类号： H04L25/067 ,  H04L1/0054 ,  H04L1/0071 ,  H04L5/0007 ,  H04L5/006 ,  H04L5/0091 ,  H04L27/38

摘要： A metric generation scheme for use in OFDM receivers. In a preferred embodiment, an OFDM receiver of the invention includes a dynamic quantizer to compress a series of channel-state information values. Also, a bit de-interleaver is provided to de-interleave a series of symbol-based data inverse to interleaving operations at a transmitter end. The de-interleaved symbol-based data is further compressed by another dynamic quantizer to yield a complex signal according to a constellation scheme. Then a metric generator calculates a bit metric of a zero group and a bit metric of a one group for each received bit in which the constellation is divided into the one group and the zero group for each bit location.

摘要翻译： 用于OFDM接收机的度量生成方案。 在优选实施例中，本发明的OFDM接收机包括用于压缩一系列信道状态信息值的动态量化器。 此外，提供了一个解交织器，用于将一系列基于符号的数据逆交换到发送器端处的交织操作。 解交织的基于符号的数据被另一个动态量化器进一步压缩，以产生根据星座图方案的复信号。 然后，度量发生器为每个接收的比特计算零组的比特量度和一组的比特度量，其中星座被划分成一个组，并且对于每个比特位置分配零组。

公开(公告)号：US08941153B2

公开(公告)日：2015-01-27

申请号：US12871655

申请日：2010-08-30

申请人： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

发明人： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC分类号： H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

摘要翻译： 集成电路结构包括包括第一器件区域中的第一部分和第二器件区域中的第二部分的半导体衬底。 第一半导体鳍片在半导体衬底之上并且具有第一鳍片高度。 第二半导体鳍片在半导体衬底之上并且具有第二鳍片高度。 第一鳍高度大于第二翅片高度。

公开(公告)号：US08796156B2

公开(公告)日：2014-08-05

申请号：US13343586

申请日：2012-01-04

申请人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

发明人： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

IPC分类号： H01L21/302

CPC分类号： H01L21/823431 ,  H01L21/845

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

公开(公告)号：US08653576B2

公开(公告)日：2014-02-18

申请号：US12648598

申请日：2009-12-29

申请人： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

发明人： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/4234

摘要： A method of forming a SONOS gate structure. The method includes forming a gate pattern with sidewalls on a substrate, wherein the gate pattern includes a gate dielectric layer patterned on the substrate and a gate electrode patterned on the gate dielectric layer, forming a first oxide layer on the gate pattern and the substrate; etching back the first oxide layer to expose the substrate and the top of the gate electrode, leaving oxide spacers along the sidewalls of the gate pattern respectively; forming a second oxide layer on the substrate and the oxide spacers; and forming trapping dielectric spacers on the second oxide layer adjacent to the sidewalls of the gate pattern respectively.

摘要翻译： 一种形成SONOS门结构的方法。 该方法包括在衬底上形成具有侧壁的栅极图案，其中栅极图案包括在衬底上图案化的栅极电介质层和在栅极电介质层上图案化的栅电极，在栅极图案和衬底上形成第一氧化物层; 蚀刻第一氧化物层以暴露衬底和栅电极的顶部，分别沿着栅极图案的侧壁留下氧化物间隔物; 在所述衬底和所述氧化物间隔物上形成第二氧化物层; 以及分别在与栅极图案的侧壁相邻的第二氧化物层上形成俘获电介质间隔物。

公开(公告)号：US08592918B2

公开(公告)日：2013-11-26

申请号：US12843658

申请日：2010-07-26

申请人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

发明人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC分类号： H01L21/02

CPC分类号： H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211

摘要： An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

摘要翻译： 集成电路结构包括具有第一器件区域中的第一部分和第二器件区域中的第二部分的衬底; 以及在第一器件区域和衬底上的两个绝缘区域。 两个绝缘区域包括具有第一k值的第一电介质材料。 半导体条在两个绝缘区之间并相邻，半导体条的顶部在两个绝缘区的顶表面上形成半导体鳍。 另外的绝缘区域位于第二器件区域和衬底之上。 附加绝缘区域包括具有大于第一k值的第二k值的第二电介质材料。

公开(公告)号：US20130237026A1

公开(公告)日：2013-09-12

申请号：US13416926

申请日：2012-03-09

申请人： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

发明人： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

IPC分类号： H01L29/78 ,  H01L21/30

CPC分类号： H01L21/265 ,  H01L21/26506 ,  H01L21/2654 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7847

摘要： A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin. The gate structure interfaces at least two sides of the fin. A stress film is formed on the substrate including on the fin. The substrate including the stress film is annealed. The annealing provides a tensile strain in a channel region of the fin. For example, a compressive strain in the stress film may be transferred to form a tensile stress in the channel region of the fin.

公开(公告)号：US20130228830A1

公开(公告)日：2013-09-05

申请号：US13411304

申请日：2012-03-02

申请人： Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Wei-Jen Lai

发明人： Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Wei-Jen Lai

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L27/0886 ,  H01L21/28088 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823431 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785

摘要： A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

公开(公告)号：US08519481B2

公开(公告)日：2013-08-27

申请号：US12612442

申请日：2009-11-04

申请人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

发明人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC分类号： H01L27/088

CPC分类号： H01L27/0203 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845

摘要： An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

摘要翻译： 集成电路结构包括：基板; 两个绝缘区域在衬底上，两个绝缘区域中的一个在其中包括空隙; 以及在所述两个绝缘区域之间并相邻的第一半导体条带。 第一半导体条包括在两个绝缘区域的顶表面上形成翅片的顶部部分。