摘要:
There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching connections among a plurality of signal lines by means of a plurality of transistors formed respectively in a plurality of semiconductor layers and a plurality of logic blocks formed in each of the plurality of semiconductor layers and connected to each of the plurality of signal lines. The first switch block is a programmable switch block capable of changing the connection topology among the plurality of signal lines.
摘要:
A testing apparatus for testing an electronic device, includes a deterministic jitter applying means for applying deterministic jitter to a given input signal without any amplitude variation component occurring and supplying the input signal applied with the deterministic jitter to the electronic device, a jitter amount controlling means for controlling magnitude of the deterministic jitter to be applied by the deterministic jitter applying means and a judging means for judging quality of the electronic device based on an output signal outputted by the electronic device in response to the input signal.
摘要:
Timing jitter sequences Δφj[n] and Δφk[n] of respective clock signals under measurement xj(t) and xk(t) are estimated, and a timing difference sequence between those timing jitter sequences is calculated. In addition, initial phase angles φ0j and φ0k of linear instantaneous phases of the xj(t) and xk(t) are estimated, respectively. A sum of a difference between those initial angles and the timing difference sequence is calculated to obtain a clock skew sequence between the xj(t) and xk(t).
摘要:
There is provided a scaling operator for calculating a quotient in a first residue format obtained by dividing an input number in the first residue format by a second modulus in a residue number system for representing numbers by the first residue format of a set of residues obtained with respect to first modulus and residues obtained with respect to second modulus, having a subtracter for outputting inter-moduli values of difference which are values of difference between the residues obtained with respect to the first modulus and the residues obtained with respect to the second modulus and a quotient outputting section for outputting a set of residues of the quotient obtained with respect to the first modulus and residues of the quotient obtained with respect to the second modulus as the quotient based on the inter-moduli values of difference.
摘要:
A jitter measuring apparatus for measuring timing jitter of a signal-under-test is provided, wherein the jitter measuring apparatus includes a pulse generator for outputting a pulse signal of a predetermined pulse width for an edge of the signal-under-test, whose timing jitter is under test; and a jitter measuring sub-unit for extracting the timing jitter on the basis of a duty ratio of each cycle of the signal output by the pulse generator.
摘要:
There is provided a jitter estimating apparatus for calculating phase noise waveform of an input signal and for estimating a peak value, a peak-to-peak value and a worst value of jitter of the input signal, and probability to generate jitter based on the phase noise waveform. Timing jitter sequence, period jitter sequence, and cycle to cycle period jitter sequence of the input signal are calculated and the peak value and the peak to peak value for each jitter, as well as probability to generate jitter may be estimated.
摘要:
A testing apparatus for testing an electronic device, includes a deterministic jitter applying means for applying deterministic jitter to a given input signal without any amplitude variation component occurring and supplying the input signal applied with the deterministic jitter to the electronic device, a jitter amount controlling means for controlling magnitude of the deterministic jitter to be applied by the deterministic jitter applying means and a judging means for judging quality of the electronic device based on an output signal outputted by the electronic device in response to the input signal.
摘要:
A signal under measurement is transformed into a complex analytic signal using a Hilbert transformer and an instantaneous phase of this analytic signal is estimated. A linear phase is subtracted from the instantaneous phase to obtain a phase noise waveform. The phase noise waveform is sampled in the proximity of a zero crossing point of a real part of the analytic signal. A differential waveform of the sample phase noise waveform is calculated to obtain a differential phase noise waveform. An RMS jitter is obtained from the phase noise waveform, and a peak-to-peak jitter is obtained from the phase noise waveform.
摘要:
A clock signal xc(t) that has been converted into a digital signal is transformed into a complex analytic signal zc(t), and an instantaneous phase &THgr; of the zc(t) is estimated. A linear phase is removed from the &THgr; to obtain a phase noise waveform &Dgr;&phgr;(t). The &Dgr;&phgr;(t) is sampled at a timing close to a zero crossing timing of the xc(t) to extract the &Dgr;&phgr;(t) sample. A root-mean-square value &sgr;t of the &Dgr;&phgr;(t) samples is obtained, and a differential waveform of the extracted &Dgr;&phgr;(t) samples is also obtained to obtain a period jitter Jp. Then a root-mean-square value &sgr;p of the Jp is obtained to calculate a correlation coefficient &rgr;tt=1−(&sgr;p2/(2&sgr;t2)). If necessary, an SNRt=&rgr;tt2/(1−&rgr;tt2) is obtained. The &rgr;tt and/or the SNRt is defined as a quality measure of a clock signal.
摘要:
There is provided an apparatus for and a method of measuring a jitter wherein a clock waveform XC(t) is transformed into an analytic signal using Hilbert transform and a varying term &Dgr;&phgr;(t) of an instantaneous phase of this analytic signal is estimated.