公开(公告)号：US07084008B2

公开(公告)日：2006-08-01

申请号：US10694347

申请日：2003-10-28

申请人： Daisuke Sakurai ,  Norihito Tsukahara

发明人： Daisuke Sakurai ,  Norihito Tsukahara

IPC分类号： H01L21/44

CPC分类号： H01L24/82 ,  H01L21/568 ,  H01L23/49855 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/97 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor element (111) with electrodes (112), and a passive element (113) with electrodes (113a) are embedded in a thermoplastic sheet base (115), which is then subjected to laser beam machining, electron beam machining or ion beam machining to expose electrodes (112 and 113a). Thereafter, a circuit pattern (119) is formed by formation of a thin film or printing of a conductive adhesive. Exposing the electrodes by laser beam machining or the like can be carried out in a short period of time and also by local treatment, thereby reducing damage to the base.

摘要翻译： 具有电极（112）的半导体元件（111）和具有电极（113a）的无源元件（113）嵌入在热塑性片材基座（115）中，然后经受激光束加工，电子束加工或离子 光束加工以暴露电极（112和113a）。 此后，通过形成薄膜或印刷导电粘合剂来形成电路图案（119）。 通过激光束加工等曝光电极可以在短时间内进行，也可以通过局部处理进行，从而减少对基底的损伤。

公开(公告)号：US20050275088A1

公开(公告)日：2005-12-15

申请号：US11147864

申请日：2005-06-08

申请人： Daisuke Sakurai ,  Kazuhiro Nishikawa ,  Norihito Tsukahara

发明人： Daisuke Sakurai ,  Kazuhiro Nishikawa ,  Norihito Tsukahara

IPC分类号： H01L21/98 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01R4/58 ,  H05K1/18

CPC分类号： H01L25/50 ,  H01L23/5384 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06593 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H05K1/185 ,  H05K1/189 ,  H05K2201/055 ,  H01L2924/00014 ,  H01L2924/00

摘要： Thinning and stacking are essential for circuit modules used for mobile devices of various kinds, smart cards, memory cards and the like. These demands make the manufacture of the circuit modules more complicated or less reliable due to delamination. A circuit module of a multilayer structure is provided which is formed by embedding semiconductor chips and passive components in a sheet made from a thermoplastic resin; folding a module sheet, which is formed of circuit blocks provided with wiring patterns thereon, at the boundaries of the circuit blocks so as to be stacked into layers; and thermal-bonding and integrating the module sheet by applying heat and pressure. As a result, a highly reliable circuit module can be manufactured in a simple manner.

摘要翻译： 变薄和堆叠对于用于各种移动设备，智能卡，存储卡等的电路模块是必不可少的。 这些要求使得电路模块的制造由于分层而更复杂或更不可靠。 提供了一种多层结构的电路模块，其通过将半导体芯片和无源部件嵌入由热塑性树脂制成的片材中而形成; 在电路块的边界处折叠由在其上设置有布线图案的电路块形成的模块片，以堆叠成层; 并通过施加热和压力进行热粘合和集成模块片。 结果，可以以简单的方式制造高可靠性的电路模块。

公开(公告)号：US20050221353A1

公开(公告)日：2005-10-06

申请号：US11059468

申请日：2005-02-16

申请人： Ayako Fujisaki ,  Noriyuki Yamamoto ,  Atsushi Mori ,  Daisuke Sakurai ,  Iwao Yamashita ,  Takahiko Kasuga

发明人： Ayako Fujisaki ,  Noriyuki Yamamoto ,  Atsushi Mori ,  Daisuke Sakurai ,  Iwao Yamashita ,  Takahiko Kasuga

IPC分类号： C12Q1/68 ,  G06F19/00 ,  G06F19/18 ,  G06F19/22 ,  G01N33/48 ,  G01N33/50

CPC分类号： G16B45/00 ,  G16B25/00 ,  G16B30/00 ,  G16B50/00

摘要： In gene expression analysis using DNA chips, the position of a probe on a genome sequence, candidates for splice variants, and the like are displayed in relation to one another. Information on the position of the probe designed for a DNA chip system on the genome sequence is retrieved by connecting to an external database and a server that manage sequence information (genome sequence, mRNA, EST, etc.) and annotation information of various organisms. Further, homologous sequences of a gene for which the probe was designed are detected by homology search program, and the candidates for splice variants obtained from the search are stored in a DNA chip database in relation to expression data.

摘要翻译： 在使用DNA芯片的基因表达分析中，探针在基因组序列上的位置，剪接变体的候选等相互显示。 通过连接到管理各种生物体的序列信息（基因组序列，mRNA，EST等）和注释信息的外部数据库和服务器来检索针对基因组序列上的DNA芯片系统设计的探针的位置的信息。 此外，通过同源性检索程序检测设计探针的基因的同源序列，将从搜索获得的剪接变体的候选物存储在DNA芯片数据库中，与表达数据相关。

公开(公告)号：US20050079707A1

公开(公告)日：2005-04-14

申请号：US10947177

申请日：2004-09-23

申请人： Norihito Tsukahara ,  Kazuhiro Nishikawa ,  Daisuke Sakurai

发明人： Norihito Tsukahara ,  Kazuhiro Nishikawa ,  Daisuke Sakurai

IPC分类号： H05K1/09 ,  H01B5/14 ,  H05K3/12 ,  H05K3/24 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/84

CPC分类号： H05K3/247 ,  H01L2924/0002 ,  H05K1/095 ,  H05K2201/0266 ,  H05K2201/035 ,  H01L2924/00

摘要： An interconnection substrate include: interconnection layer 12 region where at least first conductor layer 16 and second conductor layer 18 are vertically stacked in that order on substrate 10, first conductor layer 16 and second conductor layer 18 containing conductive particles and a binder, wherein first conductor layer 16 and second conductor layer 18 stacked in the interconnection layer 12 region have conductive particles different in average particle size from each other. As a result, only intended region can have low resistance.

摘要翻译： 互连基板包括：互连层12，其中至少第一导体层16和第二导体层18在基板10上依次垂直堆叠，第一导体层16和包含导电颗粒和粘合剂的第二导体层18，其中第一导体 堆叠在互连层12区域中的层16和第二导体层18具有彼此平均粒径不同的导电粒子。 结果，只有预期的区域可以具有低电阻。

公开(公告)号：US20050060886A1

公开(公告)日：2005-03-24

申请号：US10940933

申请日：2004-09-15

申请人： Norihito Tsukahara ,  Kazuhiro Nishikawa ,  Daisuke Sakurai

发明人： Norihito Tsukahara ,  Kazuhiro Nishikawa ,  Daisuke Sakurai

IPC分类号： H05K3/46 ,  H05K3/00 ,  G03C5/00

CPC分类号： H05K3/005 ,  H05K3/0011 ,  H05K3/4015 ,  H05K3/4644 ,  H05K2201/0108 ,  H05K2201/083 ,  H05K2201/10242 ,  H05K2203/0108 ,  H05K2203/104 ,  H05K2203/1189 ,  H05K2203/308 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165

摘要： A circuit board fabrication method comprising the steps of: forming first conductive interconnection 2 onto insulator substrate 1; applying resin film 41, which is to be interlevel insulator layer 42 for electrically insulating first conductive interconnection 2 and second conductive interconnection 6, onto insulator substrate 1; either making pillar-like member 3 stand on a prescribed position on first conductive interconnection 2 before applying resin film 41, or press fitting pillar-like member 3 into resin film 41 in such a manner as to reach either a surface vicinity of first conductive interconnection 2 or a portion of first conductive interconnection 2 after applying resin film 41; hardening resin film 41 to form interlevel insulator layer 42; pulling out pillar-like member 3 to form opening 5 in interlevel insulator layer 42; and (f) forming second conductive interconnection 6 onto interlevel insulator layer 42 in such a manner as to include opening 5.

摘要翻译： 一种电路板制造方法，包括以下步骤：在绝缘体基板1上形成第一导电布线2; 将用于将第一导电互连2和第二导电互连6电绝缘的层间绝缘体层42的树脂膜41施加到绝缘体基板1上; 在施加树脂膜41之前，使柱状构件3在第一导电布线2上的规定位置上立起，或者将柱状构件3按压到树脂膜41中，使其到达第一导电互连 2或第一导电互连2的一部分; 硬化树脂膜41以形成层间绝缘体层42; 拉出柱状构件3以在层间绝缘体层42中形成开口5; 和（f）以包括开口5的方式在层间绝缘体层42上形成第二导电布线6。